Abstract: A method for determining the integrity of navigation data of a control unit of an automotive vehicle, including the steps involving setting two counters to a value strictly above the maximum of the two counters, and, in a waking phase, calculating the fingerprints of the data written to the reset safe area, comparing the counters and determining the integrity of the data when the counters are the same.

Abstract: Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device receives data bits for storage. Based on the data bits, the memory device generates a codeword that includes the data bits, parity bits, and placeholder bits. The memory device balances the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device stores at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device is able to re-invert the appropriate packets to recover the original data bits.

Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Programmable thresholds may be configured for a memory device based on a type of data or a location of stored data, among other aspects. For example, a host device may configure a threshold quantity of errors for data at a memory device. When retrieving the data, the memory device may track or count errors in the data and determine whether the threshold has been satisfied. The memory device may transmit (e.g., to the host device) an indication whether the threshold has been satisfied, and the system may perform functions to correct the errors and/or prevent further errors. The memory device may also identify errors in received commands or may identify errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).

Abstract: Systems and methods are provided that provide protection from undesired latching that may be caused by indeterminate interamble periods in an input/output data strobe (DQS) signal. Interamble compensation circuitry selectively filters out interamble states of the DQS signal to reduce provision of interamble signals to downstream components that use the DQS signal to identify data latching times.

Abstract: The present disclosure generally relates to a method and device for simultaneously decoding data. Rather than sending data to be decoded to a single decoder, the data can be sent to multiple, available decoders so that the data can be decode in parallel. The data decoded from the first decoder that completes decoding of the data will be delivered to the host device. All remaining decoded data that was decoded in parallel will be discarded. The decoders operating simultaneously in parallel can operate using different parameters such as different calculation precision (power levels). By utilizing multiple decoders simultaneously in parallel, the full functionality of the data storage device's decoding capabilities are utilized without increasing latency.

Abstract: Error correction procedures for a memory device including a memory die having an array of memory cells including a plurality of banks are described. The memory die includes a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. The memory die further includes a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit is located under the footprint of the array and the second ECC circuit is located outside the footprint of the array.

Abstract: A testing and verification system for an equivalent physical configuration of an in-flight entertainment and communications system with one or more hardware components includes a virtual machine manager. One or more virtual machines each including a hardware abstraction layer is instantiated by the virtual machine manager according to simulated hardware component definitions corresponding to the equivalent physical configuration of the hardware components. The virtual machines are in communication with each other over virtual network connections. A test interface to the one or more virtual machines generate test inputs to target software applications installed on the virtual machines. A display interface is connected to the virtual machines, with results from the execution of the target software applications responsive to the test inputs are output thereto.

Abstract: Provided is a coding control method in a passive optical network (PON). The method includes acquiring a codeword length N corresponding to a service to be coded; acquiring a matched coding mode corresponding to the codeword length N in a preset table describing a correspondence between codeword length ranges and coding modes; and coding data of the service by using the matched coding mode. Further provided are a coding control apparatus in a PON, a communication device and a storage medium.

Abstract: Signature generation circuitry is configured to update a signature in response to each of a plurality of writes to memory. The signature is updated by performing bitwise operations between current bit values of the signature and at least some of the bits written to memory in response a write. The bitwise operation are order-independent such that the resulting signature is the same irrespective of the order in which the writes are used to update the signature. The signatures are formed in an order-independent manner such that, if no errors have occurred in generating the data to be written to be memory, the signatures will match. In this way, a compact signature is developed that is suitable export from the data processing device for checking against a corresponding data processing device of a machine running a duplicate application.

Abstract: Methods and devices for writing or for checking a controller of a vehicle are provided. A first set of vehicle parameters are written into the controller of the vehicle as coding parameters. A second set of vehicle parameters are written in another controller of the vehicle coupled to the controller via a vehicle bus of the vehicle. The first set of vehicle parameters are compared with the second set of vehicle parameters. An error is detected based on the comparing. The vehicle is not started in response to the detected error.

Abstract: A memory system includes a non-volatile memory configured to store an N-dimensional error correction code and a memory controller.

Abstract: Methods, systems, and computer-readable media for automated problem detection for machine learning models are disclosed. A machine learning analysis system receives data associated with use of a machine learning model. The data was collected by a machine learning inference system and comprises input to the model or a plurality of inferences representing output of the machine learning model. The machine learning analysis system performs analysis of the data associated with the use of the machine learning model. The machine learning analysis system detects one or more problems associated with the use of the machine learning model based at least in part on the analysis. The machine learning analysis system initiates one or more remedial actions associated with the one or more problems associated with the use of the machine learning model.

Abstract: A memory device includes a memory cell array, an input/output circuit, a test register circuit, and a test control block. The memory cell array is suitable for storing data. The input/output circuit is suitable for inputting and outputting the data stored in the memory cell array. The test register circuit is suitable for testing the input/output circuit. The test control block includes a replica circuit having a replica configuration of the test register circuit by modeling the test register circuit, and is suitable for generating the data to test the test register circuit.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, row fault detector circuitry and control logic circuitry. The memory cell array includes a plurality of memory cell rows. The control logic circuitry controls the ECC engine circuitry to perform a plurality of error detection operations on each of the memory cell rows. The control logic circuitry controls the row fault detector circuitry to store an error parameter associated with each of a plurality of codewords in each of which at least one error is detected by accumulating the error parameter for each of a plurality of defective memory cell rows. The row fault detector circuitry determines whether a row fault occurs in each of the plurality of defective memory cell rows based on a number of changes of the error parameter.

Abstract: A recording system according to the present disclosure includes a first host device, a first communication device connected to the first host device, a second host device, and a second communication device connected to the second host device. The second communication device is connected to a recording medium and wirelessly connected to the first communication device, and, when the recording medium is controlled to be writable between the second host device and the second communication device, the first communication device is configured to transmit information indicating that the recording medium is unwritable to the first host device.

Abstract: A processing device performs operations including receiving a request to locate one or more distribution edges of one or more programming distributions of a memory cell, the request specifying a target error rate for the one or more programming distributions, measuring at least one error rate sample of a first programming distribution selected from the one or more programming distributions, and determining a location of a first distribution edge of the first programming distribution at the target error rate based on a comparison of the at least one error rate sample of the first programming distribution against the target error rate.

Abstract: Provided herein is a method, an electronic device, and a computer program product for managing a storage system. A method can comprise, in response to determining that a first storage unit of a storage system is faulty, writing, by a system comprising a processor, a data block stored in the first storage unit into a hidden file of the storage system. The hidden file can be distributed across at least a second storage unit and a third storage unit of the storage system, wherein the second storage unit and the third storage unit are different from the first storage unit. Writing the data block can comprise creating the hidden file in the storage system, and creating an index information item corresponding to the data block for the hidden file, which index information item indicates a physical address of the data block.

Abstract: An encoding method includes: receiving configuration data related to encoding with a predetermined encoding mode; determining an encoding strategy based on the configuration data, wherein the encoding strategy includes parameters associated with encoding the data on an entity; and causing the data to be encoded on the entity based on the encoding strategy.

Abstract: Methods, systems and apparatus for correcting a stream of syndrome measurements produced by a quantum computer. A layered representation of error propagation through quantum error detection circuits is received. The layered representation includes a plurality of line circuit layers that each represent a probability of local detection events in a quantum computer associated with one or more potential error processes in the execution of a quantum algorithm. During execution of the quantum algorithm, one or more syndrome measurements are received from quantum error detection circuits. The syndrome measurements are converted into detection events and written to an array that represents quantum error correction circuits that are grouped together at a sequence of steps in the quantum algorithm. Errors in the execution of the quantum algorithm are determined from the detection events in dependence upon the stored line circuit layers. Based on the determined errors, the syndrome measurements are corrected.

Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to decode encoded data (e.g., data encoded using one or more encoding techniques). The neural networks and/or recurrent neural networks have nonlinear mapping and distributed processing capabilities which are advantageous in many systems employing the neural network decoders and/or recurrent neural networks. In this manner, neural networks or recurrent neural networks described herein are used to implement error correction coding (ECC) decoders.