Patents Examined by Daniel Luke
  • Hybrid FINFET/nanowire SRAM cell using selective germanium condensation
    Patent number: 9536885
    Abstract: A semiconductor device including a pFET and an nFET where: (i) the gate and conductor channel of the pFET are electrically insulated from a buried oxide layer; and (ii) the conductor channel of the nFET is in the form of a fin extending upwards from, and in electrical contact with, the buried oxide layer. Also, a method of making the pFET by adding a fin structure extending from the top surface of the buried oxide layer, then condensing germanium locally into the lattice structure of the lower portion of the fin structure, and then etching away the lower portion of the fin structure so that it becomes a carrier channel suspended above, and electrically insulated from the buried oxide layer.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Isaac Lauer, Jeffrey W. Sleight
  • Substrate structure and manufacturing method thereof
    Patent number: 9538647
    Abstract: A substrate structure is provided. The substrate structure includes a substrate and a carrier. The substrate includes a first through hole, a first surface and a second surface opposite to the first surface. The first through hole penetrates the substrate for connecting the first surface and the second surface. The carrier includes a second through hole, a release layer, an insulating paste layer and a metal layer. The insulating paste layer is disposed between the release layer and the metal layer. The carrier is attached to the second surface with the release layer thereof. The second through hole corresponds to the first through hole and penetrates the carrier for exposing the first through hole.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: January 3, 2017
    Assignee: SUBTRON TECHNOLOGY CO., LTD.
    Inventor: Chao-Min Wang
  • Nitride semiconductor substrate
    Patent number: 9530846
    Abstract: A solution is formation of a nitride semiconductor layer on one principal plane of a single crystal substrate through a first layer. Upon selecting arbitrary three places in a radial direction from a cross section cleaved in a diameter portion and observing an interface between the first layer and the nitride semiconductor layer by taking a width of at least 500 nm in the radial direction, a value is within the range of 6 nm or more and 15 nm or less in a mean value of the three places with regard to a difference between a maximum height of a convex top portion and a minimum height of a concave bottom portion of the first layer in a thickness direction from the single crystal substrate toward the nitride semiconductor layer. A value is 10 nm or more and 25 nm or less in the mean value.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: December 27, 2016
    Assignee: CoorsTek KK
    Inventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi
  • DMOS transistor with trench schottky diode
    Patent number: 9530880
    Abstract: A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: December 27, 2016
    Assignee: Micrel, Inc.
    Inventors: Jayasimha Swamy Prasad, Paul McKay Moore, David Raymond Zinn
  • Interconnection structure, semiconductor device, and method of manufacturing the same
    Patent number: 9524903
    Abstract: An interconnection structure may include insulating layers stacked stepwise and dielectric layers interposed between the insulating layers. The interconnection structure may include conductive layers interposed between the insulating layers and surrounding sidewalls of the dielectric layers, respectively. The interconnection structure may include contact plugs each coupled to one of the conductive layers. The contact plugs may at least partially pass through the dielectric layers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: December 20, 2016
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Organic light-emitting display apparatus with color filter
    Patent number: 9520452
    Abstract: In an aspect, an organic light-emitting display apparatus is provided, including: an insulating layer having a inclined structure; a first electrode disposed on the insulating layer; a selective wavelength transparent layer disposed on the first electrode; a pixel defined layer disposed on the insulating layer and the first electrode and defining an emissive region and a non-emissive region; an organic emissive layer disposed on the first electrode; and a second electrode disposed on the organic emissive layer.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: December 13, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Ik Lim, Jae-Kyoung Kim
  • Over-mold plastic packaged wide band-gap power transistors and MMICS
    Patent number: 9515011
    Abstract: A transistor package includes a lead frame, a wide band-gap transistor attached to the lead frame, and an over-mold surrounding the lead frame and the wide band-gap transistor. The wide band-gap transistor has a peak output power greater than 150 W when operated at a frequency up to 3.8 GHz. Using an over-mold along with a wide band-gap transistor in the transistor package allows the transistor package to achieve an exceptionally high efficiency, gain, and bandwidth, while keeping the manufacturing cost of the transistor package low.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: December 6, 2016
    Assignee: Cree, Inc.
    Inventors: Simon Wood, James W. Milligan, Chris Hermanson
  • Method for repairing display substrate, display substrate and display apparatus
    Patent number: 9513414
    Abstract: A method for repairing a display substrate, comprising steps of: forming a black matrix pattern on a substrate, wherein there is a first pattern missing region in the black matrix pattern; forming a color filter layer pattern on the substrate on which the black matrix pattern is formed; removing all patterns from the substrate within the first pattern missing region by laser processing the first pattern missing region of the substrate based on a position of the first pattern missing region; and filling a first repair material into the first pattern missing region of the substrate processed by laser so as to repair the first pattern missing region. The present invention also discloses a display substrate and a display apparatus.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: December 6, 2016
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Display Technology Co., Ltd.
    Inventors: Xu Wang, Ye Wang, Wenfu Zhang, Hongtao Dong
  • Pixel unit and method of fabricating the same, array substrate and display device
    Patent number: 9508755
    Abstract: The present invention provides a pixel unit including a thin film transistor and a pixel electrode, the thin film transistor includes a gate, a source and a drain, and the pixel electrode is electrically connected to the drain through a via hole. An upper end surface of the via hole is connected to the pixel electrode, and a lower end surface of the via hole is connected to the drain. The via hole is a step-shaped hole, and an area of the upper end surface of the via hole is larger than that of the lower end surface of the via hole. The present invention also provides a method of fabricating the pixel unit, an array substrate including the pixel unit, and a display device including the array substrate.
    Type: Grant
    Filed: November 28, 2013
    Date of Patent: November 29, 2016
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Xiangyong Kong, Dongfang Wang, Jun Cheng, Hongda Sun
  • Integrated vacuum microelectronic device and fabrication method thereof
    Patent number: 9508520
    Abstract: An integrated vacuum microelectronic device comprises: a highly doped semiconductor substrate, at least one insulating layer) placed above said doped semiconductor substrate, a vacuum aperture formed within said at least one insulating layer and extending to the highly doped semiconductor substrate, a first metal layer acting as a cathode, a second metal layer placed under said highly doped semiconductor substrate and acting as an anode. The first metal layer is placed adjacent to the upper edge of the vacuum aperture and the vacuum aperture has a width dimension such as the first metal layer remains suspended over the vacuum aperture.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: November 29, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Davide Giuseppe Patti
  • Methods and apparatuses having strings of memory cells and select gates with double gates
    Patent number: 9508735
    Abstract: An apparatus, a method, and a system are disclosed. The apparatus includes a string of memory cells coupled to a select gate drain transistor that has a front control gate and a back control gate. The front and back control gates can be coupled together such that they are biased at the same voltage or separate such that they can be biased at different voltages.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: November 29, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Vertically integrated wafers with thermal dissipation
    Patent number: 9508685
    Abstract: Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: November 29, 2016
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Zhijiong Luo
  • Forming multi-stack nanowires using a common release material
    Patent number: 9502500
    Abstract: A method for forming a multi-stack nanowire device includes forming a common release layer on a substrate, the common release layer comprising a common release material. The method also includes forming a first multi-layer stack on a first portion of the common release layer, the first multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material, and forming a second multi-layer stack on a second portion of the common release layer, the second multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material. The method further includes patterning each of the first multi-layer stack and the second multi-layer stack into one or more fins and forming two or more multi-stack nanowires from the one or more fins by removing the common release material using a common etch process.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Substrate processing apparatus, method of manufacturing semiconductor device and semiconductor device
    Patent number: 9496134
    Abstract: Provided is a substrate processing apparatus capable of suppressing accumulation of reaction products or decomposed matters on an inner wall of a nozzle and suppressing scattering of foreign substances in a process chamber. The substrate processing apparatus includes a process chamber, a heating unit, a source gas supply unit, a source gas nozzle, an exhaust unit, and a control unit configured to control at least the heating unit, the source gas supply unit and the exhaust unit. The source gas nozzle is disposed at a region in the process chamber, in which a first process gas is not decomposed even under a temperature in the process chamber higher than a pyrolysis temperature of the first process gas, and the control unit supplies the first process gas into the process chamber two or more times at different flow velocities to prevent the first process gas from being mixed.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: November 15, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Shinya Sasaki, Yuji Takebayashi, Shintaro Kogura
  • Three-dimensional nonvolatile memory device
    Patent number: 9496273
    Abstract: A semiconductor device includes word lines stacked in a cell region of a substrate and each of the word lines includes a first conductive layer. At least one selection line is stacked on top of the word lines and includes a second conductive layer. At least one gate line is formed in a peripheral region of the substrate and includes the second conductive layer.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: November 15, 2016
    Assignee: SK Hynix Inc.
    Inventor: Yoo Nam Jeon
  • Anti-fuse and method for forming the same
    Patent number: 9490333
    Abstract: An anti-fuse includes a first gate structure disposed in a semiconductor substrate and a second gate structure that is spaced apart from the first gate structure by a distance and disposed in the semiconductor substrate. The first and second gate structures have different depths from each other in the semiconductor substrate.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: November 8, 2016
    Assignee: SK HYNIX INC.
    Inventor: Sung Hye Park
  • Array substrate and method for manufacturing the same, display device
    Patent number: 9484364
    Abstract: An array substrate and a display device are presented. The array substrate includes: a base substrate and a plurality of thin film transistor units located on the base substrate, wherein, the thin film transistor unit includes: a first gate electrode located on the base substrate, a gate insulating layer located on the first gate electrode, a drain electrode disposed in the same layer as the first gate electrode, an active layer located on the drain electrode, a source electrode located on the active layer, a first transparent conductive layer is provided between the base substrate and the first gate electrode and the drain electrode that are disposed in the same layer, and the gate insulating layer is also disposed between the first gate electrode plus the first transparent conductive layer beneath it and the drain electrode plus the first transparent conductive layer beneath it.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: November 1, 2016
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jing Li, Wenyu Zhang, Jiaxiang Zhang
  • Contact hole collimation using etch-resistant walls
    Patent number: 9466523
    Abstract: Contact holes are constrained to their designated active areas by etch-resistant walls so that they cannot contact adjacent active areas. Etch-resistant walls provide outer limits for any contact hole bending that may occur and thus keep contact holes substantially vertical. Mask openings for contact hole formation may be large so that they overlap etch-resistant walls.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: October 11, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Tomoyasu Kakegawa, Takuya Futase, Katsuo Yamada, Keita Kumamoto, Hirotada Tobita
  • Oxide semiconductor thin film transistor with reduced impurity diffusion
    Patent number: 9455349
    Abstract: A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having small current in an off state (in a non-conductive state) is provided. A semiconductor device including such a transistor is provided. A first electrode is formed over a substrate, a first insulating layer is formed adjacent to a side surface of the first electrode, and a second insulating layer is formed to cover the first insulating layer and be in contact with at least part of a surface of the first electrode. The surface of the first electrode is formed of a conductive material that does not easily transmit an impurity element. The second insulating layer is formed of an insulating material that does not easily transmit an impurity element. An oxide semiconductor layer is formed over the first electrode with a third insulating layer provided therebetween.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: September 27, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Tetsuhiro Tanaka, Yuhei Sato, Sachiaki Tezuka, Shunpei Yamazaki
  • Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits
    Patent number: 9455201
    Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: September 27, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Manoj Joshi, Manfred Eller, Rohit Pal, Richard J. Carter, Srikanth Balaji Samavedam, Bongki Lee, Jin Ping Liu