Patents Examined by Daniel Luke
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Patent number: 9842776Abstract: Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable aspects. As may be implemented in accordance with one or more embodiments, a semiconductor wafer is provided with a plurality of integrated circuit dies and first and second opposing surfaces, and with the second surface of the wafer being ground. A first mold compound is applied to the ground second surface, and the integrated circuit dies are separated along saw lanes while using the first mold compound to hold the dies in place. The integrated circuit dies are encapsulated with the mold compounds, by applying the second mold compound to the first surface and along sidewalls of the integrated circuit dies.Type: GrantFiled: January 13, 2016Date of Patent: December 12, 2017Assignee: NXP B.V.Inventors: John Suman Nakka, Tonny Kamphuis, Roelf Anco Jacob Groenhuis
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Patent number: 9837334Abstract: Cooling devices for SOI wafers and methods for forming the devices are presented. A substrate having a top surface layer, a support substrate and an insulator layer isolating the top surface layer from the support substrate is provided. At least one device is disposed in the top surface layer of the substrate. The IC includes a cooling device. The cooling device includes a doped layer which is disposed in a top surface of the support substrate, and a RDL layer disposed within the support substrate below the doped layer for providing connections to hotspots in the doped layer to facilitate thermoelectric conduction of heat in the hotspots away from the hotspots.Type: GrantFiled: March 30, 2015Date of Patent: December 5, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Kheng Chok Tee, Juan Boon Tan, Wei Liu, Kam Chew Leong
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Patent number: 9831159Abstract: In one implementation, a semiconductor package includes a control transistor and a sync transistor of a power converter switching stage attached over a first patterned conductive carrier, as well as a magnetic material situated over leads of the first patterned conductive carrier. The semiconductor package also includes a second patterned conductive carrier attached over the first patterned conductive carrier, the control and sync transistors, and the magnetic material. Leads of the second patterned conductive carrier overlie the magnetic material and are coupled to the leads of the first patterned conductive carrier so as to form windings of an output inductor for the power converter switching stage, the output inductor being integrated into the semiconductor package.Type: GrantFiled: April 19, 2016Date of Patent: November 28, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Darryl Galipeau, Danny Clavette
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Patent number: 9818873Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.Type: GrantFiled: October 9, 2015Date of Patent: November 14, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Emre Alptekin, Lars W. Liebmann, Injo Ok, Balasubramanian Pranatharthiharan, Ravikumar Ramachandran, Soon-Cheon Seo, Charan V. V. S. Surisetty, Mickey H. Yu
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Patent number: 9812428Abstract: Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.Type: GrantFiled: October 21, 2016Date of Patent: November 7, 2017Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventor: Zhijiong Luo
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Patent number: 9812586Abstract: In a cross section in a channel width direction, a semiconductor layer includes a first region of which one end portion is in contact with an insulating layer and which is positioned at one side portion of the semiconductor layer; a second region of which one end portion is in contact with the other end portion of the first region and which is positioned at an upper portion of the semiconductor layer; and a third region of which one end portion is in contact with the other end portion of the second region and the other end portion is in contact with the insulating layer and which is positioned at the other side portion of the semiconductor layer. In the second region, an interface with a gate insulating film is convex and has three regions respectively having curvature radii R1, R2, and R3 that are connected in this order from the one end portion side toward the other. R2 is larger than R1 and R3.Type: GrantFiled: October 20, 2014Date of Patent: November 7, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 9812413Abstract: A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region adjacent to the upper surface. A recess extends from the upper surface toward the lower surface along the sidewall of the chip. A redistribution layer is electrically connected to the signal pad region and extends into the recess. A circuit board is located between the upper surface and the lower surface and extends into the recess. A conducting structure is located in the recess and electrically connects the circuit board to the redistribution layer. A method for forming the chip module is also provided.Type: GrantFiled: January 13, 2016Date of Patent: November 7, 2017Assignee: XINTEC INC.Inventors: Ho-Yin Yiu, Ying-Nan Wen, Chien-Hung Liu
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Patent number: 9799688Abstract: An array substrate includes a display area and a peripheral area adjacent to the display area; the display area includes a plurality of pixel units; each pixel unit includes a thin-film transistor (TFT) and a pixel electrode; and a drain electrode of the TFT directly contacts with the pixel electrode. In the array substrate, the drain electrode of the TFT directly contacts with the pixel electrode, and hence a uniformly distributed electric field will be generated between common electrodes and the pixel electrodes.Type: GrantFiled: June 18, 2013Date of Patent: October 24, 2017Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Xiangyang Xu, Zhuhua Nie, Liyun Deng, Minsu Kim, Kai Wang
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Patent number: 9799558Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a first dielectric layer over a substrate and forming a sacrificial layer over the first dielectric layer. The method further includes forming an opening in the sacrificial layer and etching the first dielectric layer to form a via hole through the opening. The method further includes forming a conductive structure in the via hole and the opening and removing the sacrificial layer to expose an upper portion of the conductive structure. The method further includes forming a second dielectric layer around the upper portion of the conductive material.Type: GrantFiled: November 16, 2015Date of Patent: October 24, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsi-Wen Tien, Carlos H. Diaz, Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao
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Patent number: 9793424Abstract: A photoelectric conversion device includes a substrate having a first surface and a second surface that is an opposite side of the first surface, wherein one of the first and second surfaces is a light incidence surface, a photodiode (PD) formed in the first surface of the substrate, a reflective layer formed on one of the first and second surfaces of the substrate, which is the opposite side of the light incidence surface, and a microlens formed on the light incidence surface of the substrate.Type: GrantFiled: May 6, 2015Date of Patent: October 17, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Keun-yeong Cho, Ho-chul Ji
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Patent number: 9793417Abstract: A three-terminal nano-electro-mechanical field-effect transistor (NEMFET) includes a source electrode, a gate electrode, a drain electrode and a nanoelectromechanically suspended channel bridging the source electrode and the drain electrode. The nanoelectromechanically suspended channel includes a moveable nanowire and a dielectric coating on a surface of the nanowire facing the gate electrode. A thickness of a gap between the nanowire and the gate electrode is determined by a thickness of the dielectric coating.Type: GrantFiled: April 11, 2014Date of Patent: October 17, 2017Assignee: The Regents of the University of CaliforniaInventors: Ji Hun Kim, Jie Xiang, Zack Ching-Yang Chen, Soonshin Kwon
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Patent number: 9786835Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.Type: GrantFiled: May 14, 2015Date of Patent: October 10, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Jeffrey P. Gambino, Mark D. Jaffe, Anthony K. Stamper, Randy L. Wolf
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Patent number: 9780204Abstract: A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.Type: GrantFiled: November 16, 2016Date of Patent: October 3, 2017Assignee: Micrel, Inc.Inventors: Jayasimha Swamy Prasad, Paul McKay Moore, David Raymond Zinn
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Patent number: 9780061Abstract: A method of manufacturing a molded chip package is provided which comprises arranging an electronic chip on a supporting structure; forming an isolation layer at least on portions of the electronic chip; and molding an encapsulation which covers the electronic chip and the supporting structure at least partially by using a molding material comprising a matrix material and a conductive filler material.Type: GrantFiled: May 26, 2014Date of Patent: October 3, 2017Assignee: Infineon Technologies AGInventors: Franz Gabler, Horst Theuss
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Patent number: 9780166Abstract: A method for forming a multi-stack nanowire device includes forming a common release layer on a substrate, the common release layer comprising a common release material. The method also includes forming a first multi-layer stack on a first portion of the common release layer, the first multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material, and forming a second multi-layer stack on a second portion of the common release layer, the second multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material. The method further includes patterning each of the first multi-layer stack and the second multi-layer stack into one or more fins and forming two or more multi-stack nanowires from the one or more fins by removing the common release material using a common etch process.Type: GrantFiled: March 30, 2015Date of Patent: October 3, 2017Assignee: International Business Machines CorporationInventor: Effendi Leobandung
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Patent number: 9773812Abstract: A structure includes an off-axis Si substrate with an overlying s-Si1?xGex layer and a BOX between the off-axis Si substrate and the s-Si1?xGex layer. The structure further includes pFET fins formed in the s-Si1?xGex layer and a trench formed through the s-Si1?xGex layer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-Si1?xGex layer has a value of x that results from a condensation process that merges an initial s-Si1?xGex layer with an initial underlying on-axis <100> Si layer. A method to fabricate the structure is also disclosed.Type: GrantFiled: January 10, 2017Date of Patent: September 26, 2017Assignee: International Business Machines CorporationInventors: Cheng-Wei Cheng, Pouya Hashemi, Effendi Leobandung, Alexander Reznicek
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Patent number: 9773904Abstract: A vertical field effect device includes a substrate and a vertical channel including InxGa1-xAs on the substrate. The vertical channel includes a pillar that extends from the substrate and includes opposing vertical surfaces. The device further includes a stressor layer on the opposing vertical surfaces of the vertical channel. The stressor layer includes a layer of epitaxial crystalline material that is epitaxially formed on the vertical channel and that has lattice constant in a vertical plane corresponding to one of the opposing vertical surfaces of the vertical channel that is greater than a corresponding lattice constant of the vertical channel.Type: GrantFiled: April 19, 2016Date of Patent: September 26, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Borna Obradovic, Chris Bowen, Titash Rakshit, Palle Dharmendar, Mark Rodder
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Patent number: 9773722Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact surfaces. The semiconductor package includes a top surface, a bottom surface that is opposite the top surface, and side surfaces between the top surface and the bottom surface. Each of the side surfaces includes a step such that the area of the bottom surface is smaller than the area of the top surface. The semiconductor package includes a plurality of contacts that is located at peripheral edges of the bottom surface. Each of the plurality of contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a curved surface located at a corresponding step. In some embodiments, the first surface and the curved surface are plated, while the second surface is exposed (not plated).Type: GrantFiled: May 7, 2015Date of Patent: September 26, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul, Woraya Benjavasukul
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Patent number: 9761510Abstract: A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided.Type: GrantFiled: May 7, 2015Date of Patent: September 12, 2017Assignee: XINTEC INC.Inventor: Chien-Hung Liu
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Patent number: 9761560Abstract: A display device includes a panel substrate including a pad region, and a COF (Chip On Film) including a wire region, the wire region including a plurality of wires connected to the pad region of the panel substrate, wherein the plurality of wires in the wire region is arranged into a plurality of sections, intervals between wires within each section being different from intervals between wires within an adjacent section, and at least one of the plurality of sections including a plurality of wires at a fixed interval.Type: GrantFiled: March 11, 2015Date of Patent: September 12, 2017Assignee: Samsung Display Co., Ltd.Inventors: Chung Seok Lee, Jeong Do Yang, Tae Ho Lee
