Patents Examined by Daniel Luke
  • Method of forming gate dielectric layer for MOS transistor
    Patent number: 9761687
    Abstract: A method of forming a gate dielectric layer for a MOS transistor includes the following steps. A gate dielectric layer is formed on a substrate. A nitridation process is performed on the gate dielectric layer. A multi-step post nitridation annealing process including two oxygen-containing annealing steps with different respective annealing temperatures is performed on the gate dielectric layer.
    Type: Grant
    Filed: January 4, 2015
    Date of Patent: September 12, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Han-Lin Hsu, Po-Lun Cheng, Chun-Liang Chen, Meng-Che Yeh, Shih-Jung Tu
  • LED die with barrier layer
    Patent number: 9755112
    Abstract: An LED die includes a base, and an N-typed semiconductor layer, an active layer and a P-typed semiconductor layer formed on the base that order. The LED die also includes an N-electrode and a P-electrode. The N-electrode is arranged on the N-typed semiconductor layer and electrically connected therewith. The P-electrode is arranged on the P-typed semiconductor layer and electrically connected therewith. The LED die further includes a barrier layer arranged between the P-typed semiconductor layer and the P-electrode. The barrier layer includes at least two materials of Cr, Ni and Ti. The at least two materials of Cr, Ni and Ti are stacked together to form the barrier layer.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: September 5, 2017
    Assignee: ADVANCED OPTOELECTRONICS TECHNOLOGY, INC.
    Inventors: Chien-Shiang Huang, Tzu-Chien Hung
  • Semiconductor device including transistor having offset insulating layers
    Patent number: 9754950
    Abstract: A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an active region, offset insulating layers separated from each other and formed in the active region, and a gate electrode having edges overlapping with the offset insulating layers and arranged in the active region between the offset insulating layers.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: September 5, 2017
    Assignee: SK Hynix Inc.
    Inventors: Dong Hwan Lee, Min Gyu Koo, Hyun Heo
  • Display device with bent portion in peripheral area
    Patent number: 9748505
    Abstract: A display device includes a first substrate having a display area and a first peripheral area, a second substrate having a second peripheral area, a first filler between the first substrate and the second substrate, and a first adhesive outside the first filler. The first adhesive bonds the first peripheral area and the second peripheral area. The first substrate has a first bent portion in the first peripheral area. The second substrate has a second bent portion in the second peripheral area.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: August 29, 2017
    Assignee: Japan Display Inc.
    Inventors: Takayasu Suzuki, Norio Oku
  • Semiconductor device
    Patent number: 9748231
    Abstract: A semiconductor device includes: a substrate; a first active region formed in the substrate and that includes a first region that has a first width and a second region including a second width larger than the first width and extended in a first direction; a second active region formed in the substrate and extended in parallel to the second region of the first active region; and an element isolation insulating film formed in the substrate and that partitions the first active region and the second active region, respectively, wherein the second region of the first active region or the second active region includes a depressed part depressed in a second direction that is perpendicular to the first direction in a plan view.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: August 29, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Makoto Yasuda, Taiji Ema, Mitsuaki Hori, Kazushi Fujita
  • Stress retention in fins of fin field-effect transistors
    Patent number: 9741856
    Abstract: Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, Stuart A. Sieg, John R. Sporre
  • Semiconductor sensor device
    Patent number: 9728567
    Abstract: A semiconductor sensor device is disclosed. The semiconductor sensor device includes a plurality of pixels and a phase grating structure. The phase grating structure has periodically arranged patterns and is disposed on the pixels.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: August 8, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jian-Bin Shiu, Wen-Zheng Yu
  • Termination structure for gallium nitride schottky diode
    Patent number: 9728655
    Abstract: A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: August 8, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Low thermal stress package for large area semiconductor dies
    Patent number: 9711424
    Abstract: A low thermal stress package for large area semiconductor dies. The package may include a substrate and at least one pedestal extending from the substrate, wherein the pedestal may have a mounting surface that is smaller than a mounting surface of a semiconductor die that is mounted to the pedestal. The bonded area between the die and the pedestal is therefore reduced relative to conventional semiconductor package substrates, as is the amount of thermal stress sustained by the die during thermal cycling.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: July 18, 2017
    Assignee: Littelfuse, Inc.
    Inventors: Richard J. Bono, Neil Solano
  • Method of fabricating semiconductor device using gang bonding and semiconductor device fabricated by the same
    Patent number: 9711693
    Abstract: A semiconductor device including a first lead electrode and a second lead electrode; a semiconductor stack structure disposed on the member, the semiconductor stack structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first and second conductive semiconductor layers; a first electrode electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; a plating layer configured to bond the semiconductor stack structure to the member; and a first wavelength converter that covers at least side surfaces of the semiconductor stack structure.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: July 18, 2017
    Inventors: Chung Hoon Lee, Dae Sung Kal, Ki Bum Nam
  • Semiconductor structures and fabrication method thereof
    Patent number: 9704972
    Abstract: A method is provided for fabricating transistors. The method includes providing a semiconductor substrate. The substrate has a gate film and a mask film formed on a top surface. The mask film contains implanted carbon ions. The method further includes forming a mask layer by etching the mask film and then forming a gate layer by etching through the gate film using the mask layer as a mask until the substrate is exposed. The method also includes forming a first sidewall containing implanted carbon ions on the side surface of the gate layer and the mask layer; forming a stress layer in the substrate on both sides of the gate layer and the first sidewall; and forming a source region on one side of the gate layer and the first sidewall and a drain region on the other side of the gate layer and the first side wall.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 11, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Qiuhua Han, Jie Chen
  • Display device including auxiliary lines and polarizing films, and manufacturing method thereof
    Patent number: 9703162
    Abstract: The embodiments of the present invention provide a substrate and a manufacturing method thereof, as well as a display device.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: July 11, 2017
    Assignee: Boe Technology Group Co., Ltd.
    Inventors: Xiangyan Zhang, Yanbing Wu, Wenbo Li, Pan Li, Qian Jia
  • Display device and method of manufacturing the same
    Patent number: 9698210
    Abstract: A display device and method of manufacturing the same are disclosed. In one aspect, the display device includes a first line extending in a first direction, a second line extending in a second direction, and a storage capacitor electrically connected to at least one of the first line and the second line. The first line includes a first metal pattern layer extending in the first direction, an intermediate insulating layer formed over the first metal pattern layer, and a second metal pattern layer formed over the first metal pattern layer and the intermediate insulating layer. The second metal pattern layer extends in the first direction. The first line also includes a third metal pattern layer electrically connecting the first metal pattern layer to the second metal pattern layer via a contact hole.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: July 4, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seunghwan Cho, Dohyun Kwon, Taehyun Kim, Donghwan Shim, Sungeun Lee, Iljeong Lee
  • Introducing self-aligned dopants in semiconductor fins
    Patent number: 9698018
    Abstract: A method of introducing self-aligned dopants in semiconductor fins and the resulting device are provided. Embodiments include providing semiconductor fins on first and second portions of a substrate; forming a BSG layer on side surfaces of the semiconductor fins on the first portion of the substrate; forming a first SiN layer on the BSG layer; forming a high quality oxide layer over an upper surface of the substrate, the first SiN layer and side surfaces of the semiconductor fins on the second portion of the substrate; forming a PSG layer over the high quality oxide layer on the second portion of the substrate and side surfaces of the semiconductor fins on the second portion of the substrate; and forming a second SiN layer over the high quality oxide layer and the PSG layer.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: July 4, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xintuo Dai, Haigou Huang, Jinping Liu
  • Organic light emitting display device and method of manufacturing the same
    Patent number: 9685488
    Abstract: An organic light emitting display (OLED) device that includes a first substrate and a second substrate. An organic light emitting element and a sealing member are formed between the first substrate and the second substrate. A touch panel, a block pattern, and a protective layer are formed on the second substrate. The block pattern is arranged above the sealing member to prevent a center of the sealing member from being excessively illuminated by a laser beam during a curing process.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: June 20, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang-Min Hong, Yong-Kyu Jang, Hyun-Min Hwang, Hyun-Young Kim
  • Epitaxial lift off stack having a pre-curved handle and methods thereof
    Patent number: 9679814
    Abstract: Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming an ELO thin film is provided which includes depositing an epitaxial material over a sacrificial layer on a substrate, adhering a flattened, pre-curved support handle onto the epitaxial material, and removing the sacrificial layer during an etching process. The etching process includes bending the pre-curved support handle to have substantial curvature while peeling the epitaxial material from the substrate and forming an etch crevice therebetween. Compression is maintained within the epitaxial material during the etching process. The flattened, pre-curved support handle may be formed by flattening a pre-curved support material.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: June 13, 2017
    Assignee: ALTA DEVICES, INC.
    Inventors: Melissa Archer, Harry Atwater, Thomas Gmitter, Gang He, Andreas Hegedus, Gregg Higashi, Stewart Sonnenfeldt
  • Transistor with curved active layer
    Patent number: 9680032
    Abstract: In a cross section in a channel width direction, a semiconductor layer includes a first region of which one end portion is in contact with an insulating layer and which is positioned at one side portion of the semiconductor layer; a second region of which one end portion is in contact with the other end portion of the first region and which is positioned at an upper portion of the semiconductor layer; and a third region of which one end portion is in contact with the other end portion of the second region and the other end portion is in contact with the insulating layer and which is positioned at the other side portion of the semiconductor layer. In the second region, an interface with a gate insulating film is convex and has three regions respectively having curvature radii R1, R2, and R3 that are connected in this order from the one end portion side toward the other. R2 is larger than R1 and R3.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: June 13, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Solid-state image pickup device, electronic apparatus using such solid-state image pickup device and method of manufacturing solid-state image pickup device
    Patent number: 9673249
    Abstract: A back-illuminated type solid-state image pickup device (1041) includes read circuits (Tr1, Tr2) formed on one surface of a semiconductor substrate (1042) to read a signal from a photo-electric conversion element (PD) formed on the semiconductor substrate (1042), in which electric charges (e) generated in a photo-electric conversion region (1052c1) formed under at least one portion of the read circuits (Tr1, Tr2) are collected to an electric charge accumulation region (1052a) formed on one surface side of the semiconductor substrate (1042) of the photo-electric conversion element (PD) by electric field formed within the photo-electric conversion element (PD). Thus, the solid-state image pickup device and the camera are able to make the size of pixel become very small without lowering a saturation electric charge amount (Qs) and sensitivity.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: June 6, 2017
    Assignee: Sony Corporation
    Inventors: Shin Iwabuchi, Kazuhide Yokota, Takeshi Yanagita, Yasushi Maruyama
  • Light-emitting element, light-emitting device, electronic device, and lighting device
    Patent number: 9666825
    Abstract: A light-emitting element with high reliability that can keep favorable characteristics after long-time driving is provided. In addition, a light-emitting device having a long lifetime including the light-emitting element is provided. Moreover, an electronic device and a lighting device having a long lifetime are provided. In a light-emitting element including an EL layer between a pair of electrodes, a light-emitting layer included in the EL layer has a stacked-layer structure which is different from the conventional structure, whereby the light-emitting element can keep favorable characteristics after long-time driving even in the case where carrier balance is changed over time due to driving of the light-emitting element or a light-emitting region is shifted due to the change.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: May 30, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Shogo Uesaka, Ryohei Yamaoka
  • Electronic apparatus and manufacturing method for an electronic apparatus having multiple substrates directly electrically connected through an insulating film
    Patent number: 9666627
    Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: May 30, 2017
    Assignee: Sony Corporation
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa