Abstract: An organic light emitting display device includes first and second substrates, a display unit on the first substrate, a metal layer on the first substrate and including a plurality of first straight and curved portions arranged to surround the display area, and a sealant bonding the first substrate and the second substrate, the sealant at least partially being on the metal layer and including a plurality of second straight and curved portions arranged to surround the display area, wherein the metal layer includes an inner area facing toward the display unit and an outer area outside the inner area in a width direction, the inner area in the first curved portions being thinner in the width direction than the inner area in the first straight portions.

Abstract: A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed. Embodiments include providing a gate stack, with source/drain regions at opposite sides thereof, and an STI layer on a silicon substrate; forming a TSV trench, laterally separated from the gate stack, through the STI layer and the silicon substrate; forming an isolation layer on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; forming a TSV in the TSV trench; forming a dielectric cap over the isolation layer and the TSV; and forming a source/drain contact through the dielectric cap and the isolation layer down to the source/drain contract regions.

Abstract: An image sensor pixel includes a photodiode disposed in a semiconductor material, and doped regions surrounding the photodiode, at least in part. The doped regions include a doped portion of the semiconductor material. Deep trench isolation structures are disposed in the doped regions, and surround the photodiode at least in part. The deep trench isolation structures include a SiGe layer disposed on side walls of the deep trench isolation structures, a high-k dielectric disposed on the SiGe layer, and a filler material.

Abstract: Provided is a method of forming a nanowire-based device. The method includes forming a first mask layer over a substrate; forming a first opening in the first mask layer; growing a first nanowire that protrudes through the first opening in the first mask layer, wherein the first nanowire has a first diameter; removing the first mask layer; oxidizing a sidewall of the first nanowire; etching the oxidized sidewall of the first nanowire; forming a second mask layer overlaying the substrate; removing the first nanowire thereby forming a second opening in the second mask layer; and growing a second nanowire that protrudes through the second opening in the second mask layer, wherein the second nanowire has a second diameter and the second diameter is different than the first diameter.

Abstract: A method for cleaning a substrate, such as a silicon substrate, a silicon-germanium substrate, or other silicon-containing substrate is disclosed. The method includes exposing the substrate to a first plasma configured to attack a sub-oxide on the substrate. The method also includes exposing the substrate to a second plasma configured to attack the native oxide on the substrate. The method further includes exposing the substrate to a gas containing at least one of molecular chlorine or a chlorine compound. The gas may be configured to remove at least some of the remaining native oxide and sub-oxide. After the cleaning process, the substrate may be further processed. Further processing steps may include, for example, an epitaxial growth process. An epitaxial growth process performed on a substrate cleaned according to the methods disclosed herein will exhibit few defects.

Abstract: A three dimensional semiconductor memory device includes a vertical channel structure extending in a vertical direction on a substrate; interlayer insulating layers surrounding the vertical channel structure and being stacked in the vertical direction on the substrate, gate electrodes surrounding the vertical channel structure and being disposed between the interlayer insulating layers, corners of the gate electrodes adjacent to the vertical channel structure being rounded, and auxiliary gate insulating patterns disposed between the gate electrodes and the vertical channel structure, wherein a side surface of the auxiliary gate insulating pattern is substantially coplanar with a side surface of the interlayer insulating layer in the vertical direction on the substrate.

Abstract: A flexible display substrate, a flexible organic light emitting display device, and a method of manufacturing the same are provided. The flexible display substrate comprises a flexible substrate including a display area and a non-display area extending from the display area, a first wire formed on the display area of the flexible substrate, and a second wire formed on the non-display area of the flexible substrate, wherein at least a part of the non-display area of the flexible substrate is curved in a bending direction, and the second wire formed on at least a part of the non-display area of the flexible substrate includes a first portion formed to extend in a first direction and a second portion formed to extend in a second direction.

Abstract: A silicon carbide semiconductor device includes: a substrate; a drift layer; a current dispersion layer; a base region; a source region; trenches; a gate insulation film; a gate electrode; a source electrode; a drain electrode; and a bottom layer. The current dispersion layer is arranged on the drift layer, and has a first conductive type with an impurity concentration higher than the drift layer. The bottom layer has a second conductive type, is arranged under the base region, covers a bottom of each trench including a corner portion of the bottom of the trench, and has a depth equal to or deeper than the current dispersion layer.

Abstract: A method of manufacturing a solar cell is disclosed. The method includes forming a doping region including first and second portions having different doping concentrations by ion-implanting a dopant into a semiconductor substrate and forming an electrode connected to the doping region. In the forming of the doping region, the first and second portions are simultaneously formed by the same process using a mask that is disposed at a distance from the semiconductor substrate.

Abstract: A bonding material stack for wafer-to-wafer bonding is provided. The bonding material stack may include a plurality of layers each including boron and nitrogen. In one embodiment, the plurality of layers may include: a first boron oxynitride layer for adhering to a wafer; a boron nitride layer over the first boron oxynitride layer; a second boron oxynitride layer over the boron nitride layer; and a silicon-containing boron oxynitride layer over the second boron oxynitride layer.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition.

Abstract: An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls.

Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated.

Abstract: An organic light-emitting diode (OLED) display capable of controlling light transmittance is disclosed. In one aspect, the OLED display includes a plurality of pixels, each including a first region configured to emit light and a second region configured to transmit light therethrough and a plurality of first electrodes respectively formed in the first regions of the pixels. The OLED display also includes a plurality of organic layers respectively formed over the first electrodes, a second electrode formed over all of the organic layers, and a plurality of third electrodes each formed in the second regions of the pixels. The OLED display further includes a plurality of solvents respectively placed over the third electrodes, wherein each of the solvents is configured to selectively block light and a fourth electrode formed over the solvents for all of the pixels.

Abstract: In an example, a device comprises a vertical stack of memory cells. Each memory cell of the vertical stack may include more than one memory element. A first vertical gate line may be coupled to a first one of the memory elements in each memory cell, and a second vertical gate line may be coupled to a second one of the memory elements in each memory cell. The first vertical gate line may be electrically isolated from the second vertical gate line.

Abstract: In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.

Abstract: A solid-state imaging apparatus includes a phase difference detection pixel including a photoelectric conversion section that is formed on a semiconductor substrate and configured to photoelectrically convert incident light, a waveguide configured to guide the incident light to the photoelectric conversion section, and a light-shielding section that is formed in vicinity of an opening of the waveguide and configured to shield a part of the incident light that enters the waveguide.

Abstract: In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.

Abstract: A vertical power transistor device includes a semiconductor layer of a first conductivity type, with a plurality of cylindrically-shaped dielectric regions disposed in the semiconductor layer. The cylindrically-shaped dielectric regions extend in a vertical direction from a top surface of the semiconductor layer downward. Adjacent ones of the cylindrically-shaped dielectric regions being laterally separated along a common diametrical axis by a narrow region of the semiconductor layer having a first width. Each dielectric region has a cylindrically-shaped, conductive field plate member centrally disposed therein. The cylindrically-shaped, conductive field plate member extends in the vertical direction from the top surface downward to near a bottom of the dielectric region. The dielectric region laterally separates the cylindrically-shaped, conductive field plate member from the narrow region.