Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, vertical insulated gate electrodes formed in the p-well, and n+ regions between the gate electrodes, so that vertical npn and pnp transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate electrodes, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the npn transistor to its emitter, to turn the npn transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. The p-channel MOSFET includes a Schottky source formed in the top surface of the npn transistor emitter.

Abstract: A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface opposite the first surface, a release layer is located above the first surface of the silicon handler wafer, and a layer selected from the group consisting of an adhesive layer and a redistribution layer is located on a surface of the release layer. After building-up a fan-out wafer level package on the support structure, infrared radiation is employed to remove (via laser ablation) the release layer, and thus remove the silicon handler wafer from the fan-out wafer level package.

Abstract: A semiconductor memory device according to an embodiment includes: a pair of insulating members separated from each other, the pair of insulating members extending in a first direction; a plurality of electrode films and a plurality of inter-layer insulating films disposed between the pair of insulating members and stacked alternately along a second direction, the second direction intersecting the first direction; a plurality of semiconductor pillars extending in the second direction and piercing the plurality of electrode films and the plurality of inter-layer insulating films; and a charge storage film disposed between one of the semiconductor pillars and one of the electrode films. An end portion on one of the insulating members side of a first electrode film of the electrode films is thicker than a central portion of the first electrode film between the pair of insulating members.

Abstract: A foldable display apparatus includes a flexible display panel that is foldable, and a case configured to support the flexible display panel, wherein the flexible display panel includes a first protective film at a first region corresponding to an out-folding portion, and a second protective film at a second region corresponding to an in-folding portion, wherein the in-folding portion and the out-folding portion have opposite directions of curvature, and wherein the first and second protective films include different materials.

Abstract: A fully depleted region may be used to reduce poly-to-substrate parasitic capacitance in an electronic device with poly-silicon layer. When the fully depleted region is located at least partially beneath the electronic device, an additional parasitic capacitance is formed between the fully depleted region and the substrate region. This additional parasitic capacitance is coupled in series with a first parasitic capacitance between a poly-silicon layer of the electronic device and the doped region. The series combination of the first parasitic capacitance and the additional parasitic capacitance results in an overall reduction of parasitic capacitance experience by an electronic device. The structure may include two doped regions on sides of the electronic device to form a fully depleted region based on lateral interaction of dopant in the doped regions and the substrate region.

Abstract: A magnetic junction and method for providing the magnetic junction are described. The magnetic junction resides on a substrate and is usable in a magnetic device. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The pinned layer has a pinned layer perpendicular magnetic anisotropy energy greater than a pinned layer out-of-plane demagnetization energy. The pinned layer includes a high perpendicular magnetic anisotropy (PMA) layer including at least one nonmagnetic component, a magnetic layer and a magnetic barrier layer between the high PMA layer and the magnetic layer. The magnetic barrier layer includes Co and at least one of Ta, W and Mo. The magnetic barrier layer is for blocking diffusion of the nonmagnetic component of the high PMA layer.

Abstract: A method for forming a multi-stack nanowire device includes forming a common release layer on a substrate, the common release layer comprising a common release material. The method also includes forming a first multi-layer stack on a first portion of the common release layer, the first multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material, and forming a second multi-layer stack on a second portion of the common release layer, the second multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material. The method further includes patterning each of the first multi-layer stack and the second multi-layer stack into one or more fins and forming two or more multi-stack nanowires from the one or more fins by removing the common release material using a common etch process.

Abstract: A semiconductor device includes a semiconductor substrate including, on a first surface, first trenches and a second trench linked to each of the first trenches. The semiconductor substrate includes: a p-type end layer extending from the first surface to a position closer to a second surface of the semiconductor substrate than an end of each of the first trenches on a second surface side and including a longitudinal end of each of the first trenches in a plan view of the first surface; a first p-type layer provided in a region between adjacent first trenches, and contacting the first electrode provided on the first surface; an n-type barrier layer; a second p-type layer. The second trench separates the p-type end layer from the first p-type layer and the second p-type layer.

Abstract: Semiconductor devices and methods for manufacturing a semiconductor device include a first semiconductor substrate in which a first scribe line region and a first chip region are defined, a first alignment mark inside the first semiconductor substrate and in the first scribe line region so as to be spaced apart from an upper side of the first semiconductor substrate, a second semiconductor substrate on the first semiconductor substrate and in which a second scribe line region and a second chip region are defined, and a second alignment mark inside the second semiconductor substrate and in the second scribe line region so as to be spaced apart from an upper side of the second semiconductor substrate, wherein the second semiconductor substrate is on the first semiconductor substrate so that positions of the first alignment mark and the second alignment mark correspond to each other.

Abstract: A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallisation layer is formed on the second surface of the semiconductor substrate. The metallisation layer has a thickness which is greater than the device thickness.

Abstract: A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having small current in an off state (in a non-conductive state) is provided. A semiconductor device including such a transistor is provided. A first electrode is formed over a substrate, a first insulating layer is formed adjacent to a side surface of the first electrode, and a second insulating layer is formed to cover the first insulating layer and be in contact with at least part of a surface of the first electrode. The surface of the first electrode is formed of a conductive material that does not easily transmit an impurity element. The second insulating layer is formed of an insulating material that does not easily transmit an impurity element. An oxide semiconductor layer is formed over the first electrode with a third insulating layer provided therebetween.

Abstract: The present disclosure provides semiconductor packages and methods for fabricating PoP semiconductor packages.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the first semiconductor region, a first electrode surrounded by the first semiconductor region and including a first electrode portion and a second electrode portion provided on the first electrode portion, and a first insulating section including first and second insulating portions. The second insulating portion is arranged side by side with the second electrode portion in a second direction perpendicular to a first direction from the first semiconductor region to the second semiconductor region. The first insulating portion is arranged side by side with the first electrode portion in the second direction. A length and a thickness of the first insulating portion in the first direction are greater than a length and a thickness of the second insulating portion in the first direction, respectively.

Abstract: A display device is provided including a plurality of pixels, wherein the plurality of pixels is arranged in a matrix form, wherein each of the plurality of pixels has an emission region and a transparent region, and wherein the emission region has a light-emitting element, and the transparent region has at least a part of a storage capacitor having transparency and is covered with at least one electrode of the storage capacitor, a first electrode covers the plurality of pixels, a light-emitting layer is arranged below the first electrode, a second electrode is arranged below the light-emitting layer, and the storage capacitor includes the first electrode.

Abstract: A high electron mobility transistor (HEMT) device with epitaxial layers that include a gallium nitride (GaN) layer co-doped with silicon (Si) and germanium Ge and a method of making the same is disclosed. The HEMT device includes a substrate with epitaxial layers over the substrate. An n-type gallium nitride (GaN) layer is disposed on an interface surface of the epitaxial layers, wherein the n-type GaN layer is co-doped with silicon (Si) and germanium (Ge) that provide a carrier concentration of at least 1×1020 cm?3 and a root mean square (RMS) surface roughness that is no greater than 2 nm for a contact surface of the n-type GaN layer that is interfaced with the interface surface of the epitaxial layers.

Abstract: A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) is mounted to the temporary carrier using an adhesive. The IPD includes a capacitor and a resistor and has a plurality of through-silicon vias (TSVs). A discrete component is mounted to the temporary carrier using the adhesive. The discrete component includes a capacitor. The IPD and the discrete component are encapsulated using a molding compound. A first metal layer is formed over the molding compound. The first metal layer is connected to the TSVs of the IPD and forms an inductor. The temporary carrier and the adhesive are removed, and a second metal layer is formed over the IPD and the discrete component. The second metal layer interconnects the IPD and the discrete component and forms an inductor. An optional interconnect structure is formed over the second metal layer.

Abstract: A hetero-channel FinFET device provides enhanced switching performance over a FinFET device having a silicon channel, and is easier to integrate into a fabrication process than is a FinFET device having a germanium channel. A FinFET device featuring the heterogeneous Si/SiGe channel includes a fin having a central region made of silicon and sidewall regions made of SiGe. A hetero-channel pFET device in particular has higher carrier mobility and less gate-induced drain leakage current than either a silicon device or a SiGe device. The hetero-channel FinFET permits the SiGe portion of the channel to have a Ge concentration in the range of about 25-40% and permits the fin height to exceed 40 nm while remaining stable.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The dielectric layer has a protection region and a lower portion that is between the protection region and the semiconductor substrate. The protection region contains more carbon than the dielectric layer. The semiconductor device structure also includes a conductive feature penetrating through the protection region, and a lower portion of the conductive feature is surrounded by the lower portion of the dielectric layer.

Abstract: A multijunction solar cell including an upper first solar subcell; a second solar subcell adjacent to the first solar subcell; a first graded interlayer adjacent to the second solar subcell; a third solar subcell adjacent to the first graded interlayer such that the third subcell is lattice mismatched with respect to the second subcell. A second graded interlayer is provided adjacent to the third solar subcell, and a lower fourth solar subcell is provided adjacent to the second graded interlayer, such that the fourth subcell is lattice mismatched with respect to the third subcell. An encapsulating layer composed of silicon nitride or titanium oxide disposed on the top surface of the solar cell, and an antireflection coating layer disposed over the encapsulating layer.

Abstract: Techniques for forming Cu interconnects in a dielectric are provided. In one aspect, a method of forming a Cu interconnect structure includes: forming at least one trench in a dielectric; depositing a metal liner into the trench; depositing a Mn-containing seed layer on the metal liner within the trench; annealing the Mn-containing seed layer under conditions sufficient to diffuse Mn from the Mn-containing seed layer to an interface between the dielectric and the metal liner forming a barrier layer between the dielectric and the metal liner; and depositing Cu into the trench to form the Cu interconnect, wherein the Cu is deposited into the trench after the annealing is performed. The metal liner may optionally be reflowed such that it is thicker at a bottom of the trench than along sidewalls of the trench. A Cu interconnect structure is also provided.