Abstract: In an embodiment, a method of updating a memory with a plurality of memory lines, the memory storing a tree, a plurality of buckets, and a plurality of rules, includes maintaining a copy of the memory with a plurality of memory lines. The method further includes writing a plurality of changes to at least one of the tree, the plurality of buckets, and the plurality of rules to the copy. The method further includes determining whether each of the plurality of changes is an independent write or a dependent write. The method further includes merging independent writes to the same line of the copy. The method further includes transferring updates from the plurality of lines of the copy to the plurality of lines of the memory.

Abstract: A quasi-cyclic low-density parity-check (QC-LDPC) encoder includes a Fourier transform circuit configured to receive an input message and to generate a transformed message based on the input message. The transformed message includes leading symbols with indices corresponding to leading elements of cyclotomic cosets of a finite field with respect to a subfield. The QC-LDPC encoder further includes a matrix multiplier circuit configured to multiply the leading symbols of the transformed message by leading symbols of a transformed LDPC generator matrix to generate leading symbols of transformed parity symbols associated with an LDPC codeword. The QC-LDPC encoder is configured to provide the leading symbols of the transformed parity symbols to an inverse Fourier transform circuit to generate parity information of the LDPC codeword.

Abstract: According to one embodiment, a chien search device includes n operation units configured to perform exclusive-OR operations, for each of the coefficients. Further, the chien search device includes first register configured to hold operation results of a highest order operation unit, for each of the coefficients. Furthermore, the chien search device includes exclusive-OR operation unit configured to perform exclusive-OR operations of the results of the first exclusive-OR operations of the highest order operation unit, for each of the coefficients. Moreover, the chien search device includes second register configured to hold operation results of the exclusive-OR operation unit, for each of the coefficients. The respective operation units reduce the number of stages of exclusive-OR operations by using the second register values.

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. After all messages within a RAID (Redundant Array of Independent Disk) group are programmed, it is determined whether a vertical ECC (Error Correction Code) within the RAID group has been generated. The processing unit directs a DMA (Direct Memory Access) controller to obtain the vertical ECC from a DRAM (Dynamic Random Access Memory) and store the vertical ECC to a buffer when the vertical ECC within the RAID group has been generated, thereby enabling the vertical ECC to be programmed to the storage unit.

Abstract: A method for performing error correction, an associated memory apparatus and an associated controller thereof are provided. The data used in a hard decoding period can be wholly or partially reserved, and the reserved data can be used in a soft decoding period. For example, a read operation is performed at a specific physical address of a flash memory; after an uncorrectable error of the read operation is detected, a re-read operation is performed at the specific physical address of the flash memory to obtain first data and temporarily store the first data into a volatile memory, and a hard decoding operation is performed on the first data; and after decoding failure of the hard decoding operation is detected, a soft decoding operation is performed according to the first data read from the volatile memory to perform error correction corresponding to the specific physical address.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for combining recovered portions of a data set. In one particular case, a system is disclosed that includes a stitching circuit and a data recovery circuit. The stitching circuit is operable to: receive a data set including at least a first fragment and a second fragment; replicate data from at least one of the first fragment and the second fragment as stitching values; and aggregate the first fragment with the second fragment with the stitching values between the first fragment and the second fragment to yield a combined data set. The data recovery circuit is operable to process the combined data set to yield an original data set.

Abstract: A method for data storage includes storing data in a memory that includes one or more memory units, each memory unit including memory blocks. The stored data is compacted by copying at least a portion of the data from a first memory block to a second memory block, and subsequently erasing the first memory block. Upon detecting a failure in the second memory block after copying the portion of the data and before erasure of the first memory block, the portion of the data is recovered by reading the portion from the first memory block.

Abstract: The present disclosure includes methods, devices, and systems for error detection or correction of stored signals in memory devices. An example method includes determining whether to perform error correction operations on contents of a non-volatile memory array. Determining whether to correct can include determining whether a level of errors in pre-programmed signals in the non-volatile memory array exceeds a bit error rate threshold, where the pre-programmed signals are different from the contents of the non-volatile memory array, and performing error correction on the contents of the non-volatile memory array if the level of errors exceeds the bit error rate threshold.

Abstract: Systems, methods, apparatus, and computer program products for providing forward error correction with low latency to live streams in networks are provided. One example method includes receiving source data at a first rate, outputting the source data at a rate less than the first rate, collecting the source data in a buffer, FEC decoding the source data, thereby generating decoded data; and outputting the decoded data at a rate equal to the first rate, either after collecting the source data in the buffer for a predetermined time duration or after collecting a predetermined amount of the source data in the buffer.

Abstract: An operating method of a storage device is provided. The operating method comprises the following steps. First, a first data is read from a target address of a first storage unit. Then, an assisting unit checks whether the target address is corresponding to a second data stored in a second storage unit. If the target address is corresponding to the second data, the assisting unit updates the first data according to the second data to generate an updated data. Next, an Error Correction Code (ECC) performs a decoding process on the updated data to generate a decoded data.

Abstract: A method, an electronic device and a controller for recovering an array of memory cells are provided. The method comprises the following steps. Whether a recovery control signal is received or not is determined. A retention checking procedure is executed for identifying whether a threshold voltage distribution of at least one bit of the memory cells in high threshold state is shifted or not, if the recovery control signal is received. A retention writing procedure is executed on the memory cells, if the memory cells in high threshold state do not pass the retention checking procedure.

Abstract: A method for implementing a scan chain to test a semiconductor including obtaining an initial structure of the scan chain, determining, according to function modules of the semiconductor corresponding to scan registers on the scan chain, a first scan register pair with backward dependency, adjusting a structure of the scan chain such that the first scan register pair with backward dependency becomes a scan register pair with forward dependency, when a fan-in scan register in the scan register pair with backward dependency belongs to the key subset of the fan-out scan register in the first scan register pair with backward dependency, and determining a key subset of a fan-out scan register in the first scan register pair with backward dependency, wherein when all fan-in scan registers in the key subset reflect a same logic value, an output logic value of a function module connected to the fan-out scan register is fixed.

Abstract: A method for writing data in a data storage device includes: writing data to a physical memory location in a non-volatile memory; writing, for a first time, to a location in a volatile memory corresponding to a logical address of the data, a physical address of the physical memory location of the non-volatile memory containing the data; and writing, for a second time, to the location in the volatile memory corresponding to the logical address of the data, the address of the physical memory location of the non-volatile memory containing the data. The physical address of the physical memory location is written with appended error detection code information, and the error detection code information is determined based on the logical address of the data.

Abstract: Provided is an error check and correction (ECC) circuit which includes a Chien search unit configured to determine whether there is an error in a data string. The Chien search unit includes a circuit configured to calculate a first bit string by multiplying a plurality of elements of Galois Field GF(2n) and a value of (n-k)-bit, and calculate a second bit string by multiplying the plurality of elements and a value of k-bit; and a plurality of Chien search circuits configured to combine the first bit string and the second bit string to calculate the arbitrary element. The plurality of Chien search circuits are arranged in a matrix along a row direction and a column direction. The first bit string is provided in the row direction or the column direction, and the second bit string is provided in a direction different from the direction of the first bit string.

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. In one embodiment, the systems and methods include providing a flash memory circuit including a superset of memory cells, accessing a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells, and based at least in part on determining that the group of memory cells was a last written group of memory cells, re-accessing a data set from the group of memory cells using a last written reference value to distinguish bit values in the group of memory cells.

Abstract: A system for test plural memories simultaneously includes a pattern generation part which generates a pattern signal for testing and transmits the signal to the memories, a delay part which receives data through a first data line from a first memory device that is disposed in a closest position from the delay part and a second data line from a second memory device that is disposed in a farthest position from the delay part, and a determination part which determines the result of testing by comparing the data from the first memory device and the second memory device. The delay part output the first data and the second data to the determination part simultaneously.

Abstract: A circuit with headroom monitoring includes a memory array having memory cells, a replica array, and a built-in self test circuit. The replica array has a plurality of word lines, a plurality of bit line pairs, and memory cells located at intersections of the plurality of word lines and the plurality of bit line pairs. The memory cells are of a same type as memory cells in the memory array. The built-in self test circuit is coupled to the replica array for adding a capacitance to at least one bit line of the plurality of bit line pairs, for sensing a read time of memory cells of the replica array with the capacitance so added, and for providing a headroom signal in response to the read time.

Abstract: Memory devices configured to determine if an error exists in read data and to respond to determined errors, as well as methods of operating such memory devices. In at least one embodiment, an internal controller of a memory device periodically performs internal error correction operations on stored user data and corrects user data in the memory device independently from instructions from an external memory access device. In further memory devices, an internal controller performs internal error correction operations on stored user data and adjusts trim values that define voltages to be utilized during a read operation in response to determining that the read user data comprises an error.

Abstract: A concatenated encoder is provided that includes an outer encoder, a symbol interleaver and a polar inner encoder. The outer encoder is configured to encode a data stream using an outer code to generate outer codewords. The symbol interleaver is configured to interleave symbols of the outer codewords and generate a binary stream. The polar inner encoder is configured to encode the binary stream using a polar inner code to generate an encoded stream. A concatenated decoder is provided that includes a polar inner decoder, a symbol de-interleaver and an outer decoder. The polar inner decoder is configured to decode an encoded stream using a polar inner code to generate a binary stream. The symbol de-interleaver is configured to de-interleave symbols in the binary stream to generate outer codewords. The outer decoder is configured to decode the outer codewords using an outer code to generate a decoded stream.

Abstract: Systems and methods are disclosed for correcting block errors. In particular, a system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This enables a space efficient approach for recovering from single-block data errors.