Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

Abstract: A method begins by a first computing device generating an initial routing plan that identifies network paths for transmitting encoded data slices of an encoded data segment from the first computing device to a second computing device. The method continues with the first computing device sending a plurality of subsets of encoded data slices to network paths. Within a network path, the method continues by a relay unit determining whether the network path defined by the initial routing plan requires adjusting. When the network path requires adjusting, the method continues with the relay unit establishing an adjusted network path by at least one of adding a relay unit and deleting a relay unit. The method continues with the relay unit sending, via the adjusted network path, the corresponding subset of encoded data slices to the second computing device.

Abstract: A memory device includes: a memory including a first port and a second port that are accessible; an error check and correct encoding circuit that applies an error check and correct code to data and writes them into the first port of the memory; an error check and correct decoding circuit that receives input of the data and the error check and correct code read from the first port of the memory, and corrects the inputted data in case of an error in the inputted data is detected based on the inputted error check and correct code; and a control circuit that writes the corrected data and the error check and correct code into the second port of the memory in case of the error is detected and a current access address and a previous access address to the first port of the memory are different.

Abstract: System and method embodiments are provided for managing storage systems. In an embodiment, a network component for managing data storage includes a storage interface configured to couple to a plurality of storage devices; and a vector-direct memory access (DMA) cache-exclusive OR (XOR) engine coupled to the storage interface and configured for a multiple parities convolution codes (MPCC) erasure coding to accelerate M parities parallel calculations and the erasures cross-iterations decoding, wherein a single XOR-engine with caches and a vector-DMA address generator is shared by the MPCC erasure coding engine for pipelining external dual data rate (DDR4) memory accesses, where M is a positive integer greater than two.

Abstract: A computer program product for implementing a scan chain to test a semiconductor including one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media, the program instructions including: program instructions to obtain an initial structure of the scan chain, program instructions to determine, according to function modules of the semiconductor corresponding to scan registers on the scan chain, at least one scan register pair with backward dependency, program instructions to adjust the initial structure of the scan chain such that the at least one scan register pair with backward dependency becomes a scan register pair with forward dependency, and program instructions to determine a key subset of a fan-out scan register in the at least one scan register pair with backward dependency.

Abstract: Provided are apparatuses and methods for generating and transmitting transmission frames of information data. A transmitting apparatus includes: a stream processor configured to generate a plurality of baseband frames; a frame generator configured to generate, from the plurality of baseband frames, a plurality of transmission frames which includes information data commonly provided to a fixed device and a mobile device, first parities to be used for signal processing at the fixed device, and second parities to be used for signal processing at the mobile device; and a transmitter configured to transmit the plurality of transmission frames.

Abstract: Providing access to an external memory controller to internal error correction bits from a memory device for use as metadata bits by the memory controller. In a first mode the memory device applies internal error correction bits for internal error correction at the memory device. In a second mode the memory device provides access to the internal error correction bits to the memory controller to allow the memory controller to use the data.

Abstract: A bit error in a flit transmitted over a link is determined to affect one or more particular bits of the flit based on a syndrome value associated with a cyclic redundancy check (CRC) value of the flit. The link includes a plurality of lanes. It is determined that the one or more particular bits were sent over one or more particular lanes of the link. The bit error is associated with the one or more particular lanes based on determining that the affected bits were transmitted over the particular lanes.

Abstract: Memory devices storing particular data, systems containing such memory devices and methods of testing such memory devices. The memory devices include an array of memory cells containing particular data, and control circuitry configured to control operations of the array of memory cells.

Abstract: Methods and devices for data sensing are disclosed. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.

Abstract: Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Abstract: A transmitter and receiver of a broadcasting signal and a method of processing the broadcasting signal are provided. The transmitter includes: a segmenter configured to segment an L1 signaling of a frame into a plurality of segmented L1 signalings such that each of the segmented L1 signalings has bits a number of which is equal to or smaller than a predetermined number; and an encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L1 signalings.

Abstract: Erasure encoded fragments are originally generated by applying an erasure encoding scheme to a data file. An erasure encoded fragment is subsequently generated directly from previously generated erasure encoded fragments or by reconstructing the original data file and then erasure encoding the reconstructed data file. The integrity or fidelity of such a subsequently generated erasure encoded fragment is verified by newly generating an error detection code, such as but not limited to a checksum, for the subsequently generated erasure encoded fragment, and comparing that subsequently error detection code against an error detection code previously generated for a previous or original version of the erasure encoded fragment. Each error detection code is preferably stored in association with its corresponding erasure encoded fragment and with one or more other erasure encoded fragments. Thus, each error detection code is saved in at least two locations.

Abstract: A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once.

Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

Abstract: A method including selecting a factor based on a number of bits in a codeword and a natural number and generating a model matrix including first and second matrices having data and parity bits. Hamming weights of the model matrix are not constant and Hamming weights of columns of the model matrix follow a statistical distribution dependent upon a codification rate of a channel. A compact matrix is generated by replacing elements of the model matrix equal to: 1 with a pseudo-random positive whole number; and 0 with ?1. A quasi-cyclic code is generated by replacing in the compact matrix: positive elements with identity matrices; and elements equal to ?1 with null matrices. A number of rows and columns in each of the identity and null matrices is equal to the factor. The quasi-cyclic code is applied to a word to generate a codeword, which is transmitted on the channel.

Abstract: A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction is performed on the data output by each of the input/output pads during a particular period of time.

Abstract: Techniques are disclosed relating to test equipment. In one embodiment, a method includes receiving failure information from a first test of a device under test (DUT). In this embodiment, the DUT includes a plurality of scan chains that each include a plurality of scan cells. In this embodiment, the first test is based on a first compressed test pattern. In this embodiment, the failure information does not permit a definitive determination as to which scan cell is a failing scan cell. In this embodiment, the method includes generating a plurality of compressed test patterns based on the first compressed test pattern. In this embodiment, the plurality of compressed test patterns specify one-to-one-modes. In this embodiment, the method includes performing one or more second tests of the DUT using the plurality of compressed test patterns to definitively determine one or more failing scan cells.

Abstract: A method for outputting data error status of a memory device includes generating data status indication codes indicating error status of data chunks transmitted by a memory controller, and combining the data status indication codes with corresponding data chunks to generate an output signal, and outputting the output signal to a data bus pin.