Abstract: Technologies are generally described for systems, devices and methods relating to generation of an instruction to store data. Read unit length information are identified for data. The read unit length information includes a read unit length. The data has a data length. The data length implicates a first error correction code of a first size. The read unit length relates to an amount of the data to be read as a unit from a memory. The read unit length is different from the data length. A second error correction code is determined to store the data. The second error correction code is based on the read unit length information. The second error correction code has a second size. The instruction is effective to store the second error correction code in association with the data in the memory.

Abstract: A method is disclosed for performing LDPC decoding, specifically layered min-sum decoding using a Tanner graph including check nodes (CN) and variable nodes (VN). Messages passed between nodes are quantized in a non-uniform manner. Values below a threshold are uniformly quantized whereas values above the threshold are non-uniformly quantized. A corresponding inverse-quantization is also defined.

Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.

Abstract: A method for encoding an input data block for storage in q-level cells of solid-state memory includes producing a preliminary block from the input data block by modulation encoding at least part of the input block into a first group of qary symbols via a first drift-tolerant encoding scheme, the preliminary block comprising the first group of qary symbols and any remainder of the input block not encoded via the first encoding scheme; generating parity data for the preliminary block via an error-correction encoding scheme; modulation encoding the parity data and any remainder of the input block into a second group of qary symbols via a second drift-tolerant encoding scheme; and supplying the qary symbols of the first and second groups for storage in respective q-level memory cells.

Abstract: Apparatuses and methods associated with instant syndrome computation in a layered LDPC decoder are described. In one embodiment an apparatus includes a first hardware layer configured to compute a first group of syndrome values from one or more bit values in the codeword and a second hardware layer configured to compute a second group of syndrome values from one or more bit values in the codeword. The apparatus also includes a first physical memory associated with the first hardware layer and configured to store the first group of syndrome values until the syndrome values change due to a change in a codeword bit value. The apparatus also includes a second physical memory associated with the second hardware layer and configured to store the second group of syndrome values until the syndrome values change due to a change in a codeword bit value.

Abstract: Disclosed is an optical transceiver. The optical transceiver includes a decoder for decoding an 8B10B line-coded signal; a data mapper for separating the decoded signal into block units and securing extra memory capacity by mapping a data code and a block information code onto each of the separated blocks; and an FEC encoding unit for creating a Forward Error Correction (FEC) data and mapping the FEC data onto the extra memory capacity.

Abstract: A method for encoding streaming data according to one embodiment of the present invention comprises: a step of dividing a forward error correction (FEC) source block into one or more FEC sub-blocks; a first encoding step of FEC encoding said one or more FEC sub-blocks; a second encoding step of encoding said FEC source block; and a step of generating third encoded data including first encoded data encoded in the first encoding step and second encoded data encoded in the second encoding step. According to one embodiment of the present invention, a streaming service is provided to multiple users in various environments or in a communication environment that varies according to movement or changes in a communication state. Further, a plurality of pieces of parity information is transmitted to provide a streaming service which is capable of high reliability data recovery.

Abstract: Methods, systems, and computer readable media for address and data integrity checking in flash memory operations are disclosed. One method includes, at a storage controller, generating, for an address unit, an address parity unit. The method further includes generating a command sequence including the address unit, the address parity unit, and an operation command specifying an operation to be performed on a flash memory array. The method further includes providing the command sequence to a flash memory device that includes the non-volatile memory array. The method further includes performing, by the flash memory device, an address integrity check on the address unit using the address parity unit. The method further includes determining whether or not to perform an operation specified by the command sequence based at least in part on a result of the address integrity check.

Abstract: Forward error correction (FEC) decoders, such as Low Density Parity Check (LDPC) decoders are described. Described FEC decoders minimize the number of internal bits in a layered processor of an LDPC decoder while maintaining high coding gain operation of the LDPC decoder. Minimizing the number of internal bits in a layered processor is achieved by non-linearly companding the soft information into lower precision format while maintaining the dynamic range of the data bits. Described FEC decoders may generate updated soft information having a precision that is equal to the channel precision.

Abstract: A method and decoder for early terminating decoding processes of serial concatenated coding are disclosed. The method includes the steps of providing a codeword, encoded by a first coding and a second coding sequentially; setting a maximum syndrome weight; decoding the second coding for the codeword by iterative calculations for syndromes; terminating decoding of the second coding if a number of the iterative calculations reaches a preset number or a syndrome weight of one iterative calculation is equal to or smaller than the maximum syndrome weight, otherwise repeating the decoding step and the terminating step; and decoding the first coding for the codeword.

Abstract: A packet transmission/reception method for use in a communication system is provided. The method includes generating control information corresponding to Forward Error Correction (FEC), acquiring at least one source packet to be protected using the FEC, generating at least one repair symbol with at least one repair FEC payload ID and at least one source FEC payload ID according to the at least one source packet and the control information, and transmitting the at least one source packet, the at least one repair symbol with the at least one repair FEC payload ID, and the at least one source FEC payload ID.

Abstract: The present technology relates to an information processing device and method, and a recording medium, which make it possible for a data recording system and so forth to be optimized in accordance with use. Provided are: a recording system decision unit that, on the basis of characteristics which are characteristics of data to be recorded in a recording medium, and include a lifespan value representing the retention period of the data and an error rate representing the percentage of errors assumed to be generated when the data is read, generates a plurality of recording regions of a logical device configured from the recording medium, and also decides recording systems to be applied in each of the recording regions; and a logical device initialization unit that initializes each of the recording regions of the logical device on the basis of the decided recording systems.

Abstract: A wrapping burst read determination unit determines whether or not a read request is a request of a wrapping read. If the read request is the request of the wrapping read, a memory address conversion unit extracts a plurality of addresses that includes an address in which payload data requested by the read request is stored, and designates a read out order of data from the plurality of addresses extracted. If the read request is the request of the wrapping read, a first data holding unit inputs first data read out from an address to which a forefront position in the read out order has been designated among the plurality of addresses, and stores the first data. If the read request is the request of the wrapping read, a data alignment unit, inputs trailing data read out from an address to which an end position in the read out order has been designated, and extracts payload data and an ECC which are correlated with each other from the first data and the trailing data.

Abstract: A transceiver architecture contains an encoder and a decoder for communicating high speed transmissions. The encoder modulates signal data based on an FEC code that has a symbol size that is not matched to a symbol size of a hexacode. Any code where the symbol size is less than the sample size for coding can be serially concatenated. During decoding the multilevel decoding leech lattice and FEC decoder iteratively passes their outputs back and forth to each other until the encoded bits are decoded.

Abstract: A method for encoding streaming data according to one embodiment of the present invention comprises: a step of dividing a forward error correction (FEC) source block into one or more FEC sub-blocks; a first encoding step of FEC encoding said one or more FEC sub-blocks; a second encoding step of encoding said FEC source block; and a step of generating third encoded data including first encoded data encoded in the first encoding step and second encoded data encoded in the second encoding step. According to one embodiment of the present invention, a streaming service is provided to multiple users in various environments or in a communication environment that varies according to movement or changes in a communication state. Further, a plurality of pieces of parity information is transmitted to provide a streaming service which is capable of high reliability data recovery.

Abstract: Methods, apparatuses, and computer-readable media for determining a source block size are presented. A sender transmits received media as source blocks. The sender receives a value N, a target number of packets from which a receiver can recover a source block with high fidelity; a value P?, a target packet payload size; a value O, a symbol reception overhead value; and a value R, a target upper bound on data reception overhead. The sender determines a value K, a number of symbols to be used per source block, based on the values N, P?, O and R. The source symbols of the source blocks are encoded into encoded symbols. In some cases, the encoded symbols include the source symbol, and in other cases the encoded symbols do not include the source symbols. The encoded symbols are packetized into at least N packets for transmission to the receiver.

Abstract: A method for transmitting a packet in a communication system is provided. The method includes dividing a data stream into data payloads of a predetermined size and adding a common header to each of the data payloads, to generate a source payload, adding a first Forward Error Correction (FEC) payload Identifier (ID) to the source payload and applying an FEC code thereto, to generate an FEC source packet for a source payload, adding a second FEC payload ID to at least one parity payload and applying an FEC code thereto, to generate an FEC parity packet for the at least one parity payload, and transmitting the FEC source packet and the FEC parity packet.

Abstract: An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for accessing a data set from a solid state storage device, using a data decoding circuit to apply a data decoding algorithm to the data set to yield a decoded output, where the decoded output includes at least one error, identifying at least one critical location in the data set, and estimating a voltage associated with the data in the data set corresponding to the critical location.

Abstract: The present invention is related to systems and methods for data storage compression. As an example, a system is discussed that includes a semiconductor device having a host interface, a compression circuit operable to compress a write data set received via the host interface, and a write channel circuit operable to apply an encoding algorithm to the compressed data set to yield an encoded data set.