Abstract: Low latency wireless communication applications require highly dynamic allocation of resources. Providing allocation information on a highly dynamic basis increases the overhead of control signaling for allocation. A technique known as blind decoding is used to reduce the control signaling overhead for allocation information. However, blind decoding may occasionally lead to invalid detection of allocation messages which in turn may lead to a number of problems such as wasted bandwidth, increased power consumption, reduced throughput, etc. A method and apparatus are disclosed that detect the invalid allocation messages by maintaining a record of previously received allocation messages and using it to check the validity of the newly received allocation messages.

Abstract: An apparatus comprises a 64b66b encoder configured to process operations, administration, and maintenance (OAM) information, determine a bit pattern based on the OAM information, form forward error correction (FEC) parity sync-headers based on the bit pattern, and form an FEC codeword with the FEC parity sync-headers, and a transmitter coupled to the 64b66b encoder and configured to transmit the FEC codeword. A method comprises processing OAM information, determining a bit pattern based on the OAM information, forming FEC parity sync-headers based on the bit pattern, forming an FEC codeword with the FEC parity sync-headers, and transmitting the FEC codeword. An apparatus comprises a receiver configured to receive an FEC codeword, and a 64b66b decoder coupled to the receiver and configured to extract FEC parity sync-headers from the FEC codeword, determine a bit pattern of the FEC parity sync-headers, and determine OAM information based on the bit pattern.

Abstract: A method includes counting a number of successive information frame (I-frame) retransmissions due to a guard timer expiring. A contactless front-end (CLF) transmits the I-frame to a secure element (SE) over a single wire protocol (SWP) interface. The method also includes discontinuing I-frame retransmission when the count equals a retransmission threshold. The method further includes deactivating the SWP interface.

Abstract: A circuit arrangement for determining m check bits c1, . . . , cm for k data bits u1, . . . , uk is provided, wherein the circuit arrangement includes a first subcircuit and a second subcircuit. The first subcircuit has k binary inputs for inputting the k data bits u=u1, . . . , uk and M binary outputs for outputting M binary intermediate values z1, . . . , zM determined from the data bits. The second subcircuit is configured to transform the intermediate values z1, . . . , zM into the check bits c1, . . . , cm.

Abstract: Resource mapping and coding schemes to handle bursty interference are disclosed that provide for spreading the modulated symbols for one or more transmission code words over more symbols in the time-frequency transmission stream. Certain aspects allow for the modulated symbols to be based on bits from more than one code word. Other aspects also provide for re-mapping code word transmission sequences for re-transmissions based on the number of re-transmissions requested by the receiver. Additional aspects provide for layered coding that uses a lower fixed-size constellation to encode/decode transmissions in a layered manner in order to achieve a larger-size constellation encoding. The layered encoding process allows the transmitter and receiver to use different coding rates for each coding layer. The layered encoding process also allows interference from neighboring cells to be canceled without knowledge of the actual constellation used to code the interfering neighboring signal.

Abstract: Systems, methods, and apparatuses are directed to optimizing turnaround timing of successive transactions between a host and a memory device. The host includes framing logic that generates a write frame that includes a plurality of data bits and an error bit checksum that is appended at the end of the data bits. The host further includes a bus infrastructure configured to accommodate the transfer of the write frame to the memory device and logic that defines the turnaround time to begin at a time instant that immediately follows the transfer of the data bits of the write frame. The turnaround time measures the time delay at which a succeeding write frame is to be transferred. In this manner, the turnaround time is optimized to enable the earlier initiation of successive data operations, thereby reducing the overall latency of successive back-to-back transactions.

Abstract: Second data is generated by re-reading first data using a second read voltage when a first ECC decoding to first data using a first read voltage fails. Third data is generated by performing a second ECC decoding to the second data. An error-bit-number, which is a number of bits different between the second data and the third data, is obtained when the second ECC decoding fails. The process is repeated by changing the second read voltage until the error-bit-number is smaller than a predetermined threshold value. A third ECC decoding is performed to an optimal data that is the second data read using the second read voltage, with which the error-bit-number is smaller than the predetermined threshold value.

Abstract: A method of operating a memory device is provided. The memory device includes a plurality of multi-level memory cells of which each memory cell includes L levels. Data which is expressed in a binary number is received. A P-length string is generated from the data. The P-length string is converted to a Q-length string. The Q-length string is distributed using I levels by eliminating at least one level from the L levels. P and Q represent binary bit lengths of the P-length string and the Q-length string. Q is greater than P. L represents a maximum number of levels which each multi-level memory cell has. I is smaller than L. The Q-length string is programmed into the plurality of memory cells.

Abstract: In one embodiment, a memory system is provided comprising a volatile memory, a non-volatile memory, and an error correction code (ECC) module. The ECC module is configured to encode, decode, and correct data stored in the volatile memory when the memory system enters and exits a sleep mode and is further configured to encode, decode, and correct data stored in the non-volatile memory when the memory system is in an active mode.

Abstract: Methods for use by processing modules in a dispersed storage network (DSN) to retrieve a data object stored in one of a plurality of storage generations of the DSN, each of the storage generations including a plurality of storage units. In various examples, a first retrieval request is generated to retrieve metadata addressing information. Based on the metadata addressing information, a second retrieval request is generated to retrieve the metadata. Using the metadata, a third retrieval request is then generated to retrieve at least a portion of the data object. The metadata addressing information, the metadata, and the data object may be retrieved from differing storage generations. Each of the first, second, and third retrieval requests are formatted in accordance with a read request format of the DSN, the read request format including a storage generation identifier field.

Abstract: A memory system includes: a memory controller which executes a data access process with an external device using an access unit; a first memory which is connected to the memory controller via a bus and has a first latency; and a second memory which is connected to the memory controller via a bus and has a second latency longer than the first latency. The access unit comprises a first access size assigned to the first memory and a second access size assigned to the second memory. The memory controller executes a data access process with the first memory using the first access size, and executes a data access process with the second memory using the second access size.

Abstract: In an embodiment, a method for performing forward error correction (FEC) on protected data packets is disclosed. The method involves creating a FEC table having columns for application data and columns for error-correction data (EC data). Then, a number of protected application data packets are received and placed in the FEC table. If an application data packet is received, then the application data from the packet is placed in the application data column. If an application data packet is not received, generated zeroes are placed in the application data column. Once the application data columns of the FEC table are full, EC data corresponding to the application data is received and placed in the EC data columns of the FEC table. The rows of the FEC table are then fed to the decoder for error correction.

Abstract: Apparatus and methods implemented therein use an ECC procedure to verify and correct errors in data corresponding to pre-programmed configuration data. Verification and correction is performed in a memory system comprising a non-volatile memory (NVM) and a read only memory (ROM). The NVM comprises a plurality of memory pages. On detecting a power-on reset (POR) command at the memory system, a determination is made whether the memory system has previously received the POR command from a host. When it is determined that the memory system has not previously received the POR command from the host, pre-programmed configuration data is read from the ROM and the memory system is initialized using the pre-programmed configuration data. An error correction code (ECC) is generated for the pre-programmed configuration data and the pre-programmed configuration data including the ECC is store in one of the plurality of pages of the NVM memory.

Abstract: An example system in accordance with an aspect of the present disclosure is to use local error detection (LED) and global error correction (GEC) information to check data fidelity and correct an error. The LED is to be calculated per cache line segment of data associated with a rank of a memory. Data fidelity may be checked in response to a memory read operation, based on the LED information, to identify a presence of an error and the location of the error among cache line segments of the rank. The cache line segment having the error may be corrected based on the GEC information, in response to identifying the error.

Abstract: A data storage device includes a resistance-based memory. A method includes storing a codeword into a first set of storage elements of the resistance-based memory. The codeword represents data to be stored, and the codeword includes first redundancy information associated with the data. The method further includes storing auxiliary redundancy information into a second set of storage elements of the resistance-based memory. The auxiliary redundancy information is associated with the data. The method further includes discarding the auxiliary redundancy information from the second set of storage elements while retaining the first redundancy information at the first set of storage elements.

Abstract: A method for execution by one or more processing modules of a dispersed storage network (DSN) includes storing a set of encoded data slices in an original plurality of storage units of the DSN associated as a current generation of a storage vault. The method determines whether utilization of the original plurality of storage units is greater than a utilization threshold. When the utilization of the original plurality of storage units is greater than the utilization threshold, the original plurality of storage units are updated to include at least one additional storage unit and a proper subset of the original plurality of storage units associated as the current generation of a storage vault to generate an updated plurality of storage units associated as a next generation of the storage vault. The set of encoded data slices are stored in the updated plurality of storage units of the DSN associated as the next generation of the storage vault.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to retrieve data from a non-volatile memory, and to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. Embodiments also include an apparatus, method and other techniques to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.

Abstract: A method of obtaining nuclear magnetic resonance (NMR) data from a subterranean formation may include operating a tool in a subterranean formation for generating both NMR data and NMR scaled data based upon NMR measurements of the subterranean formation. The method also includes operating the tool for encoding and transmitting both the NMR data and NMR scaled data, and receiving and decoding, above the subterranean formation, both the NMR data and NMR scaled data from the tool. The method also includes performing error-correction of the received and decoded NMR data based upon the received and decoded NMR scaled data.

Abstract: Methods of operating electronic systems having a memory include reading indications of memory block quality from a plurality of memory blocks of the memory in which a memory defect has been detected, wherein a value of the indication of memory block quality stored in a respective memory block of the plurality of memory blocks indicates a type of memory defect detected in the respective memory block, and, in response to the values of the indications of memory block quality, deeming a first portion of memory blocks of the plurality of memory blocks as usable, allocating a second portion of memory blocks of the plurality of memory blocks for storing only data of a particular type, and indicating a third portion of memory blocks of the plurality of memory blocks as defective.

Abstract: A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current.