Patents Examined by Daniel P Shook
  • Patent number: 10937980
    Abstract: The present disclosure provides a package structure of a display component and a display device. The package structure of a display component includes: a base substrate, a display component arranged on a surface of the base substrate, and an package layer covering the display component, in which the package layer includes a second inorganic layer, an organic layer, and a first inorganic layer capable of reducing amount of charges to be trapped sequentially stacked along a direction toward the display component.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 2, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Chunping Long
  • Patent number: 10930824
    Abstract: A light emitting device including a blue light emitting portion configured to emit blue light, a green light emitting portion configured to emit green light, and a red light emitting portion configured to emit red light, in which the blue light emitting portion includes a near-UV light emitting diode chip and a first wavelength conversion portion for wavelength conversion of near-UV light emitted from the near-UV light emitting diode chip, the blue light emitted from the blue light emitting portion includes a first peak wavelength in a wavelength band corresponding to near-UV light and a second peak wavelength in a wavelength band corresponding to blue light, and an intensity of the first peak wavelength is in a range of 0% to 20% of an intensity of the second peak wavelength.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 23, 2021
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventor: Bo Yong Han
  • Patent number: 10930891
    Abstract: An organic device comprising light emitting elements arranged on a substrate is provided. Each of the light emitting elements comprises, from a side of the substrate, a reflection layer, a light-shielding member, a first electrode, an organic layer including a light emitting layer, and a second electrode. The light emitting elements comprise a first element and a second element arranged adjacent to each other. A length in a second direction of a portion of the light-shielding member is longer than that of the portion in a first direction, the portion being arranged in a region where the first and second element are adjacent to each other, and the first direction is a direction in which the first and second element are arranged and the second direction is a direction perpendicular to the first direction.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: February 23, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroaki Sano, Takayuki Ito
  • Patent number: 10923672
    Abstract: A quantum dot organic light emitting diode (OLED) display panel is disclosed. A red-and-blue mixture light source is used as an OLED light source corresponding to a red sub-color-resist of a color filter, and/or a green-and-blue mixture light source is used as the OLED light source corresponding to a green sub-color-resist of the color filter. A blue light source in a color-mixture light source can trigger a red/green quantum dot material of a quantum dot photo-transfer film, and the triggered light passes through the color filter. A red/green light source in the color-mixture light source can directly pass through the color filter, thereby effectively improving the brightness of the quantum dot OLED display panel and the efficiency of a display panel and prolonging the lifetime of the display panel.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: February 16, 2021
    Inventor: Yuanyuan Li
  • Patent number: 10910311
    Abstract: A semiconductor device includes: a first stack structure; a second stack structure; a slit insulating layer located between the first stack structure and the second stack structure, the slit insulating layer extending in a first direction; a conductive plug located between the first stack structure and the second stack structure, the conductive plug including a first protrusion part protruding to the inside of the slit insulating layer; and an insulating spacer surrounding a sidewall of the conductive plug.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: February 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Ki Hong Yang, Yong Hyun Lim
  • Patent number: 10910301
    Abstract: Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Min-Tih Ted Lai, Tyler Leuten, Florence R. Pon
  • Patent number: 10897027
    Abstract: According to an embodiment of the invention, the organic EL device (100) comprises: an element substrate (20) having a substrate (1) and a plurality of organic EL elements (3) supported by the substrate; a thin film encapsulation structure (10) formed above the plurality of organic EL elements and having at least one compound layered body (10S) constituted by a first inorganic barrier layer (12), an organic barrier layer (14) in contact with the upper surface of the first inorganic barrier layer and having a plurality of solid sections spread out discretely, and a second inorganic barrier layer (16) in contact with the upper surface of the first inorganic barrier layer and the upper surfaces of the plurality of solid sections of the organic barrier layer; an organic planarization layer (42) provided above the thin film encapsulation structure and formed from a photosensitive resin; and a touch sensor layer (50) disposed above the organic planarization layer.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: January 19, 2021
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Katsuhiko Kishimoto, Yozo Narutaki
  • Patent number: 10897020
    Abstract: The present invention provides a flexible and foldable organic light-emitting diode (OLED) display device. When the flexible and foldable OLED display device is bent inward, information displayed on an organic light-emitting layer can be directly viewed through a substrate and a drive layer, without extending the flexible and foldable OLED display device, thereby improving usability of the flexible and foldable OLED display device. In addition, display areas at different positions and having different shapes are designed, so that the flexible and foldable OLED display device has more diversified appearances and functions.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: January 19, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Lei Wang, Shoucheng Wang
  • Patent number: 10896875
    Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Shiro Uchiyama
  • Patent number: 10892428
    Abstract: A flexible substrate and a manufacturing method thereof are provided according to embodiments of the present application. The flexible substrate includes a hard layer, an organic functional layer and a backplane layer which are stacked. The organic functional layer is attached to the backplane layer. A POL layer and a TP layer are included between the hard layer and the organic functional layer, and the TP layer includes a glass substrate and a conductive layer coated on a surface of the glass substrate.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: January 12, 2021
    Assignee: Yungu (Gu'an) Technology Co., Ltd.
    Inventors: Ning Lu, Wei Zhang
  • Patent number: 10892187
    Abstract: Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure provide an electronic device having a bridging via between a first metallization and a third metallization layer, the bridging via not contacting a second metallization layers. Methods of providing self-aligned bridging vias are also described.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: January 12, 2021
    Assignee: Micromaterials LLC
    Inventors: Regina Freed, Uday Mitra, Sanjay Natarajan
  • Patent number: 10879442
    Abstract: A light-emitting device according to embodiments of the invention includes a film having light transmissive property to visible light; a conductor layer formed on one surface of the film; and a light-emitting element having electrodes connected to the conductor layer via bumps protruding toward the film. The curvature of the film curved on the outer edge of a contact area of the conductor layer contacting the bumps is defined by a radius of a circle contacting the conductor layer at at least three points on the outer edge of the contact area, and the radius of this circle is 13 ?m or larger.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: December 29, 2020
    Assignee: Toshiba Hokuto Electronics Corporation
    Inventors: Naoki Takojima, Yojiro Yarimizu, Tsuyoshi Abe, Kouji Tanaka
  • Patent number: 10879206
    Abstract: A semiconductor structure includes a first substrate including a die region and a scribe line region adjacent to the die region, a through substrate via disposed in the first substrate in the scribe line region, a first connecting structure disposed over the first substrate in the die region, a second connecting structure disposed over the first substrate in the scribe line region and coupled to the through substrate via, a first bonding structure disposed over the first substrate in the die region and coupled to the first connecting structure, and a second bonding structure disposed over the first substrate in the scribe line region and coupled to the second connecting structure. The through substrate via, the second connecting structure and the second bonding structure are physically and electrically separated from the first connecting structure and the first bonding structure.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Tung-Jiun Wu
  • Patent number: 10872881
    Abstract: A microelectronic package may include stacked microelectronic dice, wherein a first microelectronic die is attached to a microelectronic substrate, and a second microelectronic die is stacked over at least a portion of the first microelectronic die, wherein the microelectronic substrate includes a plurality of pillars extending therefrom, wherein the second microelectronic die includes a plurality of pillars extending therefrom in a mirror-image configuration to the plurality of microelectronic substrate pillars, and wherein the second microelectronic die pillars are attached to microelectronic substrate pillars with an attachment material.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: December 22, 2020
    Assignee: Intel IP Corporation
    Inventor: Richard Patten
  • Patent number: 10872978
    Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Wei Yang, Chih-Chang Hung, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • Patent number: 10868013
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Patent number: 10867855
    Abstract: One or more embodiments are directed to establishing electrical connections through silicon wafers with low resistance and high density, while at the same time maintaining processability for further fabrication. Such connections through silicon wafers enable low resistance connections from the top side of a silicon wafer to the bottom side of the silicon wafer.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 15, 2020
    Assignee: Honeywell International Inc.
    Inventors: Robert E. Higashi, Son T. Lu, Elenita Chanhvongsak
  • Patent number: 10861809
    Abstract: A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 10861812
    Abstract: An electronic apparatus includes first and second packages. The first package includes a first semiconductor chip between opposing first and second surfaces of the first package, a plurality of terminals on the first semiconductor chip facing a first direction that is perpendicular to the first and second surface, the terminals including first input/output terminals and a second input/output terminal, and a plurality of bumps that are electrically connected to the plurality of first input/output terminals at positions that are directly below the first semiconductor chip in the first direction. The second package includes a second semiconductor chip provided on the second surface of the first package, a wire that electrically connects the second semiconductor chip to a conductor that is electrically connected to the second input/output terminal, and coating resin that covers the second surface of the first package, the second semiconductor chip and the wire.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: December 8, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Hideo Aoki
  • Patent number: 10854820
    Abstract: The present disclosure provides a blue organic electroluminescent device comprising: a substrate; an anode layer disposed on the substrate; a light emitting layer disposed on the anode layer, the light emitting layer being formed from a blue organic fluorescent material and a hole-type organic host material, wherein the blue organic fluorescent material is 8.0% to 25.0% by mass of the hole-type organic host material; and a cathode layer disposed on the light emitting layer.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: December 1, 2020
    Assignee: Changchun Institute of Applied Chemistry Chinese Academy of Sciences
    Inventors: Liang Zhou, Hongjie Zhang, Xuesen Zhao