Abstract: A heterogeneous chip stacking method includes providing a first chip, in which the first chip has a plurality of first convex pillar structures, and each first convex pillar structure has a first bonding pad portion; providing a second chip different from the first chip, in which the second chip has a plurality of second convex pillar structures, and each second convex pillar structures having a second bonding pad portion; placing the first chip on the second chip, in which the first bonding pad portions of the first convex pillar structures and the second bonding pad portions of the second convex pillar structures are in direct contact with each other respectively; and then applying at least one of a predetermined pressure, a predetermined temperature, and a predetermined ultrasonic frequency to tightly couple the first bonding pad portions and the second bonding pad portions with each other respectively.

Abstract: A semiconductor package includes a redistribution layer structure, a first sub-package positioned on the redistribution layer structure, a second sub-package positioned on the first sub-package, and a first encapsulant positioned on the first sub-package and encapsulating the second sub-package. The first sub-package includes a first semiconductor chip including a first chip through via and a dielectric through via electrically connected to the redistribution layer structure. The second sub-package includes a second semiconductor chip including a plurality of second chip through vias, each second chip through via electrically connected to one of the first chip through via and the dielectric through via, a third semiconductor chip positioned on the second semiconductor chip, and a fourth semiconductor chip positioned on the third semiconductor chip. Each of the second to fourth semiconductor chips is exposed at a side surface of the second sub-package and covered with the first encapsulant.

Abstract: An integrated circuit includes a first active area of a first conductivity type being coupled to an input/output (I/O) pad; a second active area of a second conductivity type, different from the first conductivity type, being coupled to a first supply voltage terminal; a plurality of first gate structures extending in a first direction to pass through the first and second active areas; and a first well of the second conductivity type extending along the first direction. The first and second active areas extend along a second direction different from the first direction in the first well, and the first active area is aligned with the second active area along the first direction.

Abstract: A light-emitting device having high heat resistance in a manufacturing process is provided.

Abstract: A method for producing a via in a III-V multijunction solar cell that comprises a substrate arranged on an underside. The substrate has an upper side and an epitaxial layer system with multiple III-V layers on the upper side, and the epitaxial layer system comprises at least one first III-V solar cell. An organic layer is arranged on the upper side of the first III-V solar cell, and an opening having a width X and a base surface formed in the epitaxial layer system is generated in a first method step with a laser. An opening having a width Y and having a base surface is generated in a second method step, width Y being smaller than width X, and an opening having a width Z is generated in a third method step, the opening not having a base surface, and width Z being smaller than width Y.

Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a front surface and a rear surface is provided. A plurality of trenches extending into the substrate from the front surface of the substrate is formed. A polishing stop structure is formed at a bottom of each of the plurality of trenches. The plurality of trenches is filled with a gap-filling material layer. The rear surface of the substrate is subjected to a polishing process to remove a portion of the substrate from the rear surface until the polishing stop structure is exposed.

Abstract: A light emitting element includes: a substrate; an n layer provided over the substrate as defined herein; a first active layer provided over the n layer as defined herein; a middle layer provided over the first active layer as defined herein; a second active layer provided over the middle layer as defined herein; a groove having a depth reaching the middle layer from a side of the second active layer; a first p layer provided over the second active layer as defined herein; and a second p layer provided over the middle layer exposed on a bottom surface of the groove as defined herein, and a non-n layer including a group III nitride semiconductor and containing O or Si and a p-type impurity is provided between the second active layer and the first p layer and between the middle layer and the second p layer.

Abstract: A light-emitting device with high heat resistance in a manufacturing process is to be provided.

Abstract: A semiconductor memory device includes a memory layer and a via-wiring extending in a first direction. The memory layer includes a semiconductor layer electrically connected to the via-wiring, a gate electrode including parts opposed to surfaces of the semiconductor layer on one side and the other side in the first direction, a memory portion disposed on one side in a second direction with respect to the semiconductor layer, and a wiring disposed on the other side in the second direction with respect to the semiconductor layer. In a cross-sectional surface perpendicular to the first direction and including one of the parts of the gate electrode, the via-wiring includes a surface opposed to the gate electrode and a surface not opposed to the gate electrode. A part of the gate electrode is disposed on a memory portion side with respect to the via-wiring in the second direction.

Abstract: An infrared photodiode includes an anode, a cathode, a photoelectric conversion layer between the anode and the cathode and including an infrared absorbing material, and a first auxiliary layer between the anode and the photoelectric conversion layer and a second auxiliary layer between the cathode and the photoelectric conversion layer. The first auxiliary layer and the second auxiliary layer each independently include an electron transport material that is configured to facilitate electron introduction, and/or facility electron transport, and/or inhibit hole movement. A sensor may include the infrared photodiode. An electronic device may include the infrared photodiode.

Abstract: A semiconductor package may include a substrate; at least one controller chip on the substrate; at least one chip structure on the substrate, the at least one chip structure including a buffer chip, an upper chip stack on the buffer chip, and a lower chip stack below the buffer chip; an upper wire electrically connecting the upper chip stack, the buffer chip, and the at least one controller chip; a lower wire electrically connecting the lower chip stack and the at least one controller chip; a connection wire electrically connecting the at least one controller chip to the substrate; and connection bumps below the substrate, the connection bumps being electrically connected to the at least one controller chip and the at least one chip structure.

Abstract: A deep trench resistor structure and methods of forming the same are described. The structure includes a first trench located in a first dielectric material, a first layer disposed over the first dielectric material, a second layer disposed on the first layer, a second dielectric material disposed over the second layer, and a tunable device in contact with the first layer. The tunable device includes a semiconductor-containing layer in contact with the first layer, a dielectric layer disposed on the semiconductor-containing layer, and a metal-containing layer disposed on the dielectric layer.

Abstract: A light-emitting element comprises a substrate, a light shielding layer, a capping layer and a plurality of protrusions. The light shielding layer is above the substrate. The capping layer is above the light shielding layers. The plurality of protrusions is arranged over the substrate, an organic light-emitting unit comprising an organic material being disposed between two adjacent protrusions of the plurality of protrusions. An edge of the light shielding layer is misaligned with an edge of one of the plurality of protrusions. The organic light-emitting unit includes a first light-emitting unit and a second light-emitting unit. The first light-emitting unit and the second light-emitting unit respectively have an organic light-emitting stack layer comprising an organic material.

Abstract: Provided are methods of fabricating photodetectors based on heterostructures comprising graphene and mercury chalcogenide, e.g., HgTe, quantum dots. Embodiments of the methods are able to provide photodetectors that can detect MWIR light, e.g., greater than 3 mm at room temperature with responsivities R* of at least 104 A/W and detectivities D* of at least 1011 Jones. Thus, the present photodetectors outperform existing MWIR photodetectors without the need for cooling. The photodetectors themselves are also encompassed.

Abstract: A phase-change memory device and method of manufacturing the same, the memory device including: a substrate; a bottom electrode disposed over the substrate; a top electrode disposed over the bottom electrode; and a phase-change layer disposed between the top and bottom electrodes. The phase change layer includes a chalcogenide Ge—Sb—Te (GST) material that includes at least 30 at % Ge and that is doped with a dopant including N, Si, Sc, Ga, C, or any combination thereof.

Abstract: A high-resolution display apparatus is provided. The display apparatus includes a first light-emitting device, a second light-emitting device positioned next to the first light-emitting device, a third light-emitting device positioned next to the second light-emitting device, a first insulating layer, and a second insulating layer. The first insulating layer includes a first region between the first light-emitting device and the second light-emitting device and a second region between the second light-emitting device and the third light-emitting device. The second insulating layer includes a region positioned over a lower electrode of the third light-emitting device. A thickness of a third organic compound layer of the third light-emitting device is different from a thickness of a first organic compound layer of the first light-emitting device.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate has a display area, an edge area arranged on at least one side of the display area, and a transition area arranged between the display area and the edge area, the display substrate includes: a base substrate, a plurality of sub-pixels and a redundant line located on the base substrate, the plurality of sub-pixel being arranged in an array in the display area, the redundant line extending along a column direction of the sub-pixels and passing through the transition area; each sub-pixel includes: a pixel driving circuit; the pixel driving circuit includes a storage capacitor; at least a part of second electrodes of storage capacitors extend from the display area to the transition area and are electrically connected with the redundant line.

Abstract: Provided is a method of dicing a wafer, the method including preparing a wafer having a plurality of device formation regions and a scribe lane region defining the plurality of device formation regions, forming a plurality of semiconductor devices in the plurality of device formation regions of the wafer, irradiating a first laser beam and a second laser beam of a wavelength different from the first laser beam along the scribe lane region to form a plurality of internal cracks in the wafer, and separating the plurality of semiconductor devices along the plurality of internal cracks, wherein the first laser beam includes a plurality of pulses sequentially emitted from a laser apparatus, and the second laser beam is continuous wave light emitted from the laser apparatus.

Abstract: A display apparatus includes a device substrate with a display area and a bezel area, an upper planarization layer on the device substrate, an upper interlayer insulating layer between the device substrate and the upper planarization layer, a dam pattern, a light-emitting device, a pad portion on the bezel area, link wirings extending across the display area and the bezel area between the device substrate and the upper interlayer insulating layer, and a power voltage supply line on the upper interlayer insulating layer. The power voltage supply line may include a main wiring and an external connecting wiring. The main wiring may be spaced apart from the encapsulating dam. The external connecting wiring is electrically connected to the main wiring.

Abstract: A display panel and a manufacture method thereof are provided in embodiments of the present disclosure, and the display panel includes at least one photosensitive element each including a first electrode, a photosensitive semiconductor layer and a second electrode. The photosensitive semiconductor layer is disposed on the first electrode, and the second electrode is disposed on the photosensitive semiconductor layer. The photosensitive element further includes a connection insulation layer disposed between the second electrode and the photosensitive semiconductor layer. In the present application, leakage current in a dark state is lowered and an uniformity of different photosensitive elements is improved.