Abstract: A display panel includes a base substrate; and a light-emitting device layer, disposed on the base substrate and including sub-pixels. A sub-pixel includes light-emitting regions and a non-light-emitting regions located between adjacent light-emitting regions. The display panel includes a light-shielding layer, disposed on the side of the light-emitting device layer away from the base substrate and including a light-shielding structure located in the non-light-emitting region; and a polarizer, disposed on the side of the light-shielding layer away from the base substrate and having an absorption axis in a first direction. In each sub-pixel, along the first direction, the minimum distance between the boundary of the light-emitting region and the light-shielding structure is a first distance B; along a second direction intersected with the first direction, the minimum distance between the boundary of the light-emitting region and the light-shielding structure is a second distance A; and B>A.

Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.

Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.

Abstract: A display device includes a first substrate and a second substrate at which a display area for displaying an image and a non-display area surrounding the display area are provided; a light-emitting diode in the display area on an inner surface of the first substrate and including an anode electrode, a light-emitting layer and a cathode electrode; and a piezoelectric element in the display area on an inner surface of the second substrate and including a first electrode, a piezoelectric layer and a second electrode, wherein the piezoelectric layer includes dichroic dyes.

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

Abstract: In an example, the present invention provides a method of manufacturing a solar module. The method includes providing a substrate member having a surface region, the surface region comprising a spatial region, a first end strip comprising a first edge region and a first interior region, the first interior region comprising a first bus bar, a plurality of strips, a second end strip comprising a second edge region and a second interior region, the second edge region comprising a second bus bar, the first end strip, the plurality of strips, and the second end strip arranged in parallel to each other and occupying the spatial region such that the first end strip, the second end strip, and the plurality of strips consists of a total number of five (5) strips. The method includes separating each of the plurality of strips, arranging the plurality of strips in a string configuration, and using the string in the solar module.

Abstract: A display panel includes a plurality of light-emitting elements. Light emitted from a first light-emitting element has a CIE 1931 chromaticity coordinate x of greater than 0.680 and less than or equal to 0.720 and a CIE 1931 chromaticity coordinate y of greater than or equal to 0.260 and less than or equal to 0.320. Light emitted from a second light-emitting element has a CIE 1931 chromaticity coordinate x of greater than or equal to 0.130 and less than or equal to 0.250 and a CIE 1931 chromaticity coordinate y of greater than 0.710 and less than or equal to 0.810. Light emitted from a third light-emitting element has a CIE 1931 chromaticity coordinate x of greater than or equal to 0.120 and less than or equal to 0.170 and a CIE 1931 chromaticity coordinate y of greater than or equal to 0.020 and less than 0.060.

Abstract: A direct bonding method for infrared focal plane arrays, includes steps of depositing a thin adhesion layer on infrared radiation detecting material, removing a portion of the thin adhesion layer with a chemical-mechanical polishing process, forming a bonding layer at a bonding interface, and bonding the infrared radiation detecting material to a silicon wafer with the thin adhesion layer as a bonding layer. The thin adhesion layer may include SiOx, where x ranges between 1.0 and 2.0. The thickness of the thin adhesion layer to form the bonding layer is 500 angstrom or less.

Abstract: A semiconductor device includes: a first stack structure; a second stack structure; a slit insulating layer located between the first stack structure and the second stack structure, the slit insulating layer extending in a first direction; a conductive plug located between the first stack structure and the second stack structure, the conductive plug including a first protrusion part protruding to the inside of the slit insulating layer; and an insulating spacer surrounding a sidewall of the conductive plug.

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

Abstract: The embodiments provide a process for easily producing an electrode having low resistance, easily subjected to post-process and hardly impairing the device; and also provide, as its application, a production process for a photoelectric conversion device. The process comprises the steps of: coating a hydrophobic substrate directly with a dispersion of metal nanomaterial, to form a metal nanomaterial layer, coating the surface of the metal nanomaterial layer with a dispersion of carbon material, to form a carbon material layer and thereby to form an electrode layer comprising a laminate of the metal nanomaterial layer and the carbon material layer, pressing the carbon material layer onto a hydrophilic substrate so that the surface of the carbon material layer may be directly fixed on the hydrophilic substrate, and peeling away the hydrophobic substrate so as to transfer the electrode layer onto the hydrophilic substrate.

Abstract: A solid-state imaging element including: a photoelectric conversion layer, a first electrode and a second electrode opposed to each other with the photoelectric conversion layer interposed therebetween, a semiconductor layer provided between the first electrode and the photoelectric conversion layer, an accumulation electrode opposed to the photoelectric conversion layer with the semiconductor layer interposed therebetween, an insulating film provided between the accumulation electrode and the semiconductor layer, and a barrier layer provided between the semiconductor layer and the photoelectric conversion layer.

Abstract: An SOI semiconductor structure, including a substrate layer formed on a back side and a semiconductor layer of a second conductivity type formed on a front side, an insulating layer being disposed between the substrate layer and the semiconductor layer, a three-dimensional Hall sensor structure having a sensor region made up of a monolithic semiconductor body being formed in the semiconductor layer, and the semiconductor body extending from an underside up to the front side, at least three first metallic terminal contacts being formed on the upper side, and at least three second metallic terminal contacts being formed on the underside, the first terminal contacts being offset with respect to the second terminal contacts in a projection perpendicular to the front side, each first terminal contact and each second terminal contact being formed in each case on a highly doped semiconductor contact region of a second conductivity type.

Abstract: A microelectronic package may include stacked microelectronic dice, wherein a first microelectronic die is attached to a microelectronic substrate, and a second microelectronic die is stacked over at least a portion of the first microelectronic die, wherein the microelectronic substrate includes a plurality of pillars extending therefrom, wherein the second microelectronic die includes a plurality of pillars extending therefrom in a mirror-image configuration to the plurality of microelectronic substrate pillars, and wherein the second microelectronic die pillars are attached to microelectronic substrate pillars with an attachment material.

Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. The air gap has a cross-section of substantially bottle shape with a flat top. A porous dielectric layer is disposed over the substrate, sealing the flat top of the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.

Abstract: A method of making a semiconductor device includes: providing a substrate; forming an insulating layer on the substrate; forming a first trench in the insulating layer; forming a first semiconductor layer in the first trench; and removing a portion of the insulating layer to expose the first semiconductor layer.

Abstract: According to an embodiment of the invention, the organic EL device (100) comprises: an element substrate (20) having a substrate (1) and a plurality of organic EL elements (3) supported by the substrate; a thin film encapsulation structure (10) formed above the plurality of organic EL elements and having at least one compound layered body (10S) constituted by a first inorganic barrier layer (12), an organic barrier layer (14) in contact with the upper surface of the first inorganic barrier layer and having a plurality of solid sections spread out discretely, and a second inorganic barrier layer (16) in contact with the upper surface of the first inorganic barrier layer and the upper surfaces of the plurality of solid sections of the organic barrier layer; an organic planarization layer (42) provided above the thin film encapsulation structure and formed from a photosensitive resin; and a touch sensor layer (50) disposed above the organic planarization layer.

Abstract: An ink used in forming a functional layer of a self-luminous element by a printing method, the ink including a functional material and a mixed solvent. The mixed solvent includes solvents each having different vapor pressures. The functional material is dissolved or dispersed in the mixed solvent. A solvent that has a lowest vapor pressure among the solvents has a viscosity of at least 53 mPa·s, and a viscosity of the mixed solvent is 15 mPa·s or less.

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.