Abstract: A semiconductor package may include a substrate; at least one controller chip on the substrate; at least one chip structure on the substrate, the at least one chip structure including a buffer chip, an upper chip stack on the buffer chip, and a lower chip stack below the buffer chip; an upper wire electrically connecting the upper chip stack, the buffer chip, and the at least one controller chip; a lower wire electrically connecting the lower chip stack and the at least one controller chip; a connection wire electrically connecting the at least one controller chip to the substrate; and connection bumps below the substrate, the connection bumps being electrically connected to the at least one controller chip and the at least one chip structure.

Abstract: A deep trench resistor structure and methods of forming the same are described. The structure includes a first trench located in a first dielectric material, a first layer disposed over the first dielectric material, a second layer disposed on the first layer, a second dielectric material disposed over the second layer, and a tunable device in contact with the first layer. The tunable device includes a semiconductor-containing layer in contact with the first layer, a dielectric layer disposed on the semiconductor-containing layer, and a metal-containing layer disposed on the dielectric layer.

Abstract: A light-emitting element comprises a substrate, a light shielding layer, a capping layer and a plurality of protrusions. The light shielding layer is above the substrate. The capping layer is above the light shielding layers. The plurality of protrusions is arranged over the substrate, an organic light-emitting unit comprising an organic material being disposed between two adjacent protrusions of the plurality of protrusions. An edge of the light shielding layer is misaligned with an edge of one of the plurality of protrusions. The organic light-emitting unit includes a first light-emitting unit and a second light-emitting unit. The first light-emitting unit and the second light-emitting unit respectively have an organic light-emitting stack layer comprising an organic material.

Abstract: A phase-change memory device and method of manufacturing the same, the memory device including: a substrate; a bottom electrode disposed over the substrate; a top electrode disposed over the bottom electrode; and a phase-change layer disposed between the top and bottom electrodes. The phase change layer includes a chalcogenide Ge—Sb—Te (GST) material that includes at least 30 at % Ge and that is doped with a dopant including N, Si, Sc, Ga, C, or any combination thereof.

Abstract: Provided are methods of fabricating photodetectors based on heterostructures comprising graphene and mercury chalcogenide, e.g., HgTe, quantum dots. Embodiments of the methods are able to provide photodetectors that can detect MWIR light, e.g., greater than 3 mm at room temperature with responsivities R* of at least 104 A/W and detectivities D* of at least 1011 Jones. Thus, the present photodetectors outperform existing MWIR photodetectors without the need for cooling. The photodetectors themselves are also encompassed.

Abstract: A high-resolution display apparatus is provided. The display apparatus includes a first light-emitting device, a second light-emitting device positioned next to the first light-emitting device, a third light-emitting device positioned next to the second light-emitting device, a first insulating layer, and a second insulating layer. The first insulating layer includes a first region between the first light-emitting device and the second light-emitting device and a second region between the second light-emitting device and the third light-emitting device. The second insulating layer includes a region positioned over a lower electrode of the third light-emitting device. A thickness of a third organic compound layer of the third light-emitting device is different from a thickness of a first organic compound layer of the first light-emitting device.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate has a display area, an edge area arranged on at least one side of the display area, and a transition area arranged between the display area and the edge area, the display substrate includes: a base substrate, a plurality of sub-pixels and a redundant line located on the base substrate, the plurality of sub-pixel being arranged in an array in the display area, the redundant line extending along a column direction of the sub-pixels and passing through the transition area; each sub-pixel includes: a pixel driving circuit; the pixel driving circuit includes a storage capacitor; at least a part of second electrodes of storage capacitors extend from the display area to the transition area and are electrically connected with the redundant line.

Abstract: Provided is a method of dicing a wafer, the method including preparing a wafer having a plurality of device formation regions and a scribe lane region defining the plurality of device formation regions, forming a plurality of semiconductor devices in the plurality of device formation regions of the wafer, irradiating a first laser beam and a second laser beam of a wavelength different from the first laser beam along the scribe lane region to form a plurality of internal cracks in the wafer, and separating the plurality of semiconductor devices along the plurality of internal cracks, wherein the first laser beam includes a plurality of pulses sequentially emitted from a laser apparatus, and the second laser beam is continuous wave light emitted from the laser apparatus.

Abstract: A display apparatus includes a device substrate with a display area and a bezel area, an upper planarization layer on the device substrate, an upper interlayer insulating layer between the device substrate and the upper planarization layer, a dam pattern, a light-emitting device, a pad portion on the bezel area, link wirings extending across the display area and the bezel area between the device substrate and the upper interlayer insulating layer, and a power voltage supply line on the upper interlayer insulating layer. The power voltage supply line may include a main wiring and an external connecting wiring. The main wiring may be spaced apart from the encapsulating dam. The external connecting wiring is electrically connected to the main wiring.

Abstract: A display panel and a manufacture method thereof are provided in embodiments of the present disclosure, and the display panel includes at least one photosensitive element each including a first electrode, a photosensitive semiconductor layer and a second electrode. The photosensitive semiconductor layer is disposed on the first electrode, and the second electrode is disposed on the photosensitive semiconductor layer. The photosensitive element further includes a connection insulation layer disposed between the second electrode and the photosensitive semiconductor layer. In the present application, leakage current in a dark state is lowered and an uniformity of different photosensitive elements is improved.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a gate structure on the barrier layer, a gate spacer on the gate structure, and a gate contact on the gate spacer. The gate contact includes a first portion and a second portion respectively at two sides of the gate spacer and directly contacting the gate structure.

Abstract: Discussed in an organic light emitting display apparatus, which can include a plurality of pixels on a substrate, each pixel including a plurality of subpixels, and each of the plurality of subpixels having an emission region, a planarization layer including a light extraction pattern, the light extraction pattern disposed at the emission region of each of the plurality of subpixels and including a plurality of concave portions; and a light emitting device layer on the light extraction pattern of each of the plurality of subpixels. The emission region of each of the plurality of subpixels includes a reference point disposed at a concave portion of the plurality of concave portions. The light extraction pattern of each of the plurality of subpixels has a rotation angle with respect to the reference point.

Abstract: A photodetector focal plane array (FPA) with enhanced detection capability and reduced thermal current is provided. The FPA includes light-concentrating dielectric structures in a form of arrays of elements with three-dimensional geometrical shapes. The elements have tapered sidewalls that taper inwardly toward a surface portion with a reduced width. A photodetector is joined to the portion with a reduced width. A metallic layer is disposed over the tapered sidewalls of the elements and the portion of the surface of the elements with a reduced width. The metallic layer provides mirror reflection properties to concentrate electromagnetic fields towards the detectors. The photodetector focal plane array may be used for infrared (IR) imaging applications in mid-wave IR (MWIR) and long-wave IR (LWIR) cameras as night vision and thermal imaging devices.

Abstract: Provided are a display panel and a display device. The display panel includes: a via hole penetrating through the display panel; a cutting residual area on the periphery of the via hole and includes a base substrate, and a packaging layer: and at least one annular relief structure between the packaging laver and the base substrate in the cutting residual area. The at least one annular relief structure is sequentially distributed around the via hole. At least one relief structure is provided with a surface facing away from the base substrate, and a side face connected to the surface, at least one of the surface and the side face is of a relief shape. The first relief structure is the relief structure with a smallest distance from the center of the via hole.

Abstract: A light-emitting device and a manufacturing method thereof, a display substrate and a display apparatus are provided in the embodiments of the present disclosure. The light-emitting device includes: a first electrode disposed on a base substrate; a quantum dot light-emitting layer disposed at a side of the first electrode away from the base substrate; and an electron transport layer disposed at a side of the quantum dot light-emitting layer close to or away from the first electrode, the electron transport layer including a first transport sub-layer and a second transport sub-layer which are arranged in layer configuration, a material of the first transport sub-layer and a material of the second transport sub-layer both including n-type metal oxides, and an oxygen content of the first transport sub-layer being less than an oxygen content of the second transport sub-layer.

Abstract: A semiconductor device includes a substrate, an interconnect, a memory cell, and a plurality of first barrier structures. The interconnect is disposed over the substrate. The memory cell is disposed in the interconnect within a memory region of the substrate, where the memory cell includes a transistor and a capacitor. The transistor includes a gate, source/drain elements respectively standing at two opposite sides of the gate, and a channel disposed between the source/drain elements and overlapped with the gate. The capacitor is disposed over the transistor and electrically coupled to one of the source/drain elements. The plurality of first barrier structures line sidewalls and bottom surfaces of the source/drain elements, and each include a first barrier layer and a second barrier layer disposed between the source/drain elements and the first barrier layer, where a first absorption interface is disposed between the first barrier layer and the second barrier layer.

Abstract: A semiconductor device includes a first source region, a first sidewall body region, a gate region, a second source region and a link region formed in a substrate of a first conductivity type. The first source region and the second source region may be of the first conductivity type while the first sidewall body region and the link region may be of a second conductivity type opposite to the first conductivity type. The link region and the gate region are respectively disposed at a first side and a second side of the first source region. The first sidewall body region may be disposed below or underneath the first source region.

Abstract: A semiconductor device includes a first source region, a first sidewall body region, a gate region, a second source region and a link region formed in a substrate of a first conductivity type. The first source region and the second source region may be of the first conductivity type while the first sidewall body region and the link region may be of a second conductivity type opposite to the first conductivity type. The link region and the gate region are respectively disposed at a first side and a second side of the first source region. The first sidewall body region may be disposed below or underneath the first source region.

Abstract: A non-dispersive ligand-containing portion containing a monodentate ligand that is coordinated to a QD to render the QD non-dispersible in a solvent is formed in a part of a QD film containing the QD, and a portion of the QD film other than the non-dispersive ligand-containing portion is removed by a solvent to form a QD layer pattern.

Abstract: A method for manufacturing a semiconductor device includes preparing a substrate of a first conductivity type having a drain region, forming a first source region and a second source region of the first conductivity type in the substrate separated from each other, and forming a gate trench of a gate region disposed closely next to or in adjoining neighbor to the first source region. The method may further include forming a first sidewall body region of a second conductivity type to separate the first source region from the second source region, forming a link region of the second conductivity type such that the link region and the gate trench are disposed spatially opposite to each other, forming a gate insulation layer to coat and line sidewalls and a bottom of the gate trench, and using a gate conductive material to fill the gate trench.