Patents Examined by Daniel P Shook
  • Patent number: 10483123
    Abstract: A method for forming a well providing access to a sensor pad includes patterning a first photoresist layer over a dielectric structure disposed over the sensor pad; etching a first access into the dielectric structure and over the sensor pad, the first access having a first characteristic diameter; patterning a second photoresist layer over the dielectric structure; and etching a second access over the dielectric structure and over the sensor pad. The second access has a second characteristic diameter. The first and second accesses overlapping. A diameter ratio of the first characteristic diameter to the second characteristic diameter is not greater than 0.7. The first access exposes the sensor pad. The second access has a bottom depth less than a bottom depth of the first access.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: November 19, 2019
    Assignee: LIFE TECHNOLOGIES CORPORATION
    Inventors: Phil Waggoner, Jordan Owens
  • Patent number: 10483217
    Abstract: Representative implementations of devices and techniques provide reinforcement for a carrier or a package. A reinforcement layer is added to a surface of the carrier, often a bottom surface of the carrier that is generally under-utilized except for placement of terminal connections. The reinforcement layer adds structural support to the carrier or package, which can be very thin otherwise. In various embodiments, the addition of the reinforcement layer to the carrier or package reduces warpage of the carrier or package.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: November 19, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Sangil Lee, Craig Mitchell, Gabriel Z. Guevara, Javier A. Delacruz
  • Patent number: 10483198
    Abstract: Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Min-Tih Ted Lai, Tyler Leuten, Florence R. Pon
  • Patent number: 10468527
    Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Wei Yang, Chih-Chang Hung, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • Patent number: 10461143
    Abstract: A transistor substrate may include a base substrate, a data line, a conductive layer, a semiconductor layer, a gate electrode, and a pixel electrode. The data line may directly contact the base substrate. The conductive layer may directly contact the base substrate and may be spaced from the data line. The semiconductor layer may overlap the conductive layer, may be spaced from the conductive layer, and may include a source electrode and a drain electrode. The source electrode may be electrically connected to the data line. The gate electrode may overlap the semiconductor layer. The pixel electrode may be electrically connected to the drain electrode.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 29, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae Hyun Park, Sang Kyung Lee, Jong Moo Huh
  • Patent number: 10446393
    Abstract: A method for forming a silicon-containing epitaxial layer is disclosed. The method may include, heating a substrate to a temperature of less than approximately 950° C. and exposing the substrate to a first silicon source comprising a hydrogenated silicon source, a second silicon source, a dopant source, and a halogen source. The method may also include depositing a silicon-containing epitaxial layer wherein the dopant concentration within the silicon-containing epitaxial layer is greater than 3×1021 atoms per cubic centimeter.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: October 15, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Nupur Bhargava, John Tolle, Joe Margetis, Matthew Goodman, Robert Vyne
  • Patent number: 10439144
    Abstract: The present invention relates to: an organic compound represented by a combination of Chemical Formulas 1 and 2; an organic optoelectronic device comprising the organic compound; and a display device.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: October 8, 2019
    Assignee: UNIVERSITY-INDUSTRY COOPERATEON GROUP OF KYUNG HEE UNIVERSITY
    Inventors: JongWook Park, JaeHyun Lee
  • Patent number: 10439059
    Abstract: A transistor includes a first gate-controlled region having a first threshold voltage and a second gate-controlled region in parallel with the first gate-controlled region. The second gate-controlled region has a second threshold voltage different form the first threshold voltage.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 8, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Tomas Apostol Palacios, Sameer Jayanta-Joglekar, Ujwal Radhakrishna
  • Patent number: 10438888
    Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Shiro Uchiyama
  • Patent number: 10431616
    Abstract: Methods, systems, apparatus, including computer-readable media storing executable instructions, for color filter arrays for image sensors. In some implementations, an imaging device includes a color filter array arranged to filter incident light. The color filter array has a repeating pattern of color filter elements. The color filter elements include yellow filter elements, green filter elements, and blue filter elements. The imaging device includes an image sensor having photosensitive regions corresponding to the color filter elements. The photosensitive regions are configured to respectively generate electrical signals indicative of intensity of the color-filtered light at the photosensitive regions. The imaging device includes one or more processors configured to generate color image data based on the electrical signals from the photosensitive regions.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 1, 2019
    Assignee: Google LLC
    Inventors: Jyrki A. Alakuijala, Zoltan Szabadka
  • Patent number: 10431553
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface, which includes an element forming region and an element isolation region, and a second surface opposite to the first surface, a semiconductor element formed on the semiconductor substrate in the element forming region, an insulator formed on the semiconductor substrate in the element isolation region, a first wiring layer formed on the first surface of the semiconductor substrate, the first wiring layer being connected to the semiconductor element, an alignment mark formed on the semiconductor substrate in the element isolation region, the entire alignment mark overlapping with the insulator in a plan view of the semiconductor device, and a second wiring layer formed on the second surface of the semiconductor substrate.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: October 1, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Azusa Ozawa
  • Patent number: 10431689
    Abstract: The disclosure discloses a thin film transistor and a display panel. The thin film transistor includes a gate, a source, a drain, an active layer, and a heat transmitting layer; wherein the heat transmitting layer is arranged on a side of the active layer. In the disclosure, the heat of the active layer may be promptly conducted to the surrounding environment, so as to prevent the self-heating effect of the thin film transistor from affecting the normal working state.
    Type: Grant
    Filed: November 23, 2017
    Date of Patent: October 1, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xiao Wang
  • Patent number: 10431611
    Abstract: A method for manufacturing a thin film transistor, a method for manufacturing an array substrate, an array substrate, and a display device are provided. The method for manufacturing the thin film transistor includes: forming an active layer on a base substrate; forming a metal layer on the surface of the active layer; and processing the metal layer using a patterning process for one time and an oxidation treatment process, so that the metal layer forms a source electrode, a drain electrode and a passivation layer; wherein the source electrode and the drain electrode are in contact with the active layer, and the passivation layer is formed on a side of the source electrode and the drain electrode away from the active layer.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: October 1, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xianxue Duan, Kui Gong
  • Patent number: 10424753
    Abstract: The invention relates to production method of PEDOT:PSS film which comprises the steps of preparing substrate, preparing the mixture of boric acid doped PEDOT:PSS prepare on the substrate surface.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: September 24, 2019
    Inventors: Orhan Icelli, Serap Gunes, Sureyya Aydin Yuksel, Serco Serkis Yesilkaya, Ozlem Yagci
  • Patent number: 10424637
    Abstract: A method of manufacturing a semiconductor device that includes a semiconductor layer of a first conductivity type, and a parallel pn layer formed on the semiconductor layer, the pn layer having first semiconductor regions of the first conductivity type and second semiconductor regions of a second conductivity type, the first and second regions being alternately arranged parallel to a surface of the semiconductor layer. In one embodiment, the method includes repeatedly performing the following steps to stack the epitaxial growth layers on the semiconductor layer to form the pn layer: forming an epitaxial growth layer of the first conductivity type or non-doped, the epitaxial growth layer having an impurity concentration lower than that of the semiconductor layer, ion implanting a first-conductivity-type impurity into the epitaxial growth layer, selectively ion implanting a second-conductivity-type impurity into the epitaxial growth layer and ion implanting a group 18 element into the epitaxial growth layer.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: September 24, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shuhei Tatemichi, Shunji Takenoiri
  • Patent number: 10424610
    Abstract: A capacitor, an image sensor circuit and fabricating methods are provided. The method includes providing a base substrate including a trench region and a body region adjacent to the trench region. The method also includes forming a first trench structure and a second trench structure on the first trench structure, in the base substrate in the trench region. In addition, the method includes forming a dielectric layer on a sidewall surface and a bottom surface of the first trench structure and an electrode layer on the dielectric layer in the first trench structure. Further, the method includes forming an isolation layer filling the second trench structure.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: September 24, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Xin Liang, Chong Wang
  • Patent number: 10421721
    Abstract: The present specification relates to a hetero-cyclic compound and an organic light emitting device including the same.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: September 24, 2019
    Assignee: LG Chem, Ltd.
    Inventors: Yongbum Cha, Jin Joo Kim, Sung Kil Hong, Sang Duk Suh
  • Patent number: 10418445
    Abstract: In a vertical MOSFET having a trench gate structure, a lifetime killer region is provided in a p-type epitaxial layer formed by epitaxial growth. The lifetime killer region includes an electron lifetime killer that causes electrons entering the lifetime killer region to recombine and become extinct. As a result, the lifetime killer region decreases the electrons generated at the pn interface of the p-type epitaxial layer and an n-type drift layer and enables a configuration in which electrons are not delivered to the p-type epitaxial layer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: September 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Mina Ryo, Takeshi Tawara, Masaki Miyazato, Masaaki Miyajima
  • Patent number: 10418367
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.
    Type: Grant
    Filed: July 8, 2018
    Date of Patent: September 17, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Ching Chang, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10410926
    Abstract: The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: September 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, Pouya Hashemi