Patents Examined by Daniel P Shook
  • Patent number: 10784196
    Abstract: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via parallel to the first surface of the substrate, wherein the first conductive line includes a second surface at least partially interfaced with the conductive via, the second surface of the first conductive line includes a first end, a second end opposite to the first end and a first central axis passing through the first end and the second end, the cross section of the conductive via includes a second central axis parallel to the first central axis and a third central axis orthogonal to the second central axis.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Ta Lu, Chi-Ming Tsai
  • Patent number: 10784237
    Abstract: In a method for fabricating an emissive display, a package substrate with a top thereof having a plurality of wells is firstly provided. The well has a first electrode region and a second electrode region at different heights. The package substrate sinks in a suspension. Then, a plurality of light-emitting diodes sinks in the suspension. The light-emitting diode has a plane and a curved surface. Finally, the suspension horizontally jets such that the suspension flows across the plane and the curved surface of the light-emitting diode at different velocities. According to the different velocities, the suspension respectively embeds all the light-emitting diodes into all the wells. Each of the plurality of light-emitting diodes are respectively electrically connected to the first electrode region and the second electrode region of a corresponding one of the plurality of wells, thereby forming an emissive display.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: September 22, 2020
    Assignees: INTERFACE TECHNOLOGY (CHENGDU) CO., LTD., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventor: Chin-Feng Chung
  • Patent number: 10773947
    Abstract: An apparatus includes a MEMS wafer with a device layer and a handle substrate bonded to the device layer. A complementary metal-oxide semiconductor (“CMOS”) wafer includes an oxide layer, and a passivation layer overlying the oxide layer. A bonding electrode overlies the passivation layer. A eutectic bond is between a first bonding metal on the bonding electrode and a second bonding metal on the MEMS wafer. A sensing electrode overlies the passivation layer. A shield electrode is adjacent to the sensing electrode. A sensing gap is positioned between the sensing electrode and the device layer, wherein the sensing gap is smaller than a shield gap positioned between the shield electrode and the device layer.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: September 15, 2020
    Assignee: InvenSense, Inc.
    Inventor: Daesung Lee
  • Patent number: 10777778
    Abstract: With chemically-strengthened thin glass substrates provided with an alkali barrier film, if the light-absorbing or light-scattering nature of the alkali barrier film itself has lowered the light extraction efficiency, or if the surface of the alkali barrier film is insufficiently flat, there may consequently be an increase in leakage current of an organic EL element and a decrease in reliability, leaving room for improvement. Instead of such an alkali barrier film, by providing an organic EL panel with a barrier film of the present invention and also with an organic EL element on a chemically-strengthened thin glass substrate with a specific light extraction structure therebetween, the glass substrate having one principal surface that includes a smooth region of the present invention, a high-performance organic EL panel can be obtained without compromising the organic EL properties.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: September 15, 2020
    Assignee: KANEKA CORPORATION
    Inventor: Takayuki Miyoshi
  • Patent number: 10777679
    Abstract: A vertical transistor that includes a gate structure containing a work function metal liner that is wing-free is provided. The wing-free work function metal liner is provided by recessing a sacrificial material layer portion that is located adjacent to a work function metal liner having a winged surface near the channel and fin ends. The recessed sacrificial material layer portion allows for multi-directional etching of the winged surface of the work function metal liner and thus the wing surface can be removed forming a wing-free work function metal liner. The vertical transistor of the present application has reduced parasitic capacitance and a reduced tendency of electrical shorting between a top source/drain structure and the gate structure. The method of the present application can improve device yield.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Soon-Cheon Seo, Injo Ok, Alexander Reznicek
  • Patent number: 10773951
    Abstract: An apparatus includes a MEMS wafer with a device layer and a handle substrate bonded to the device layer. The apparatus also includes a CMOS wafer including an oxide layer, and a passivation layer overlying the oxide layer. A bonding electrode overlies the passivation layer and a bump stop electrode overlies the passivation layer. A eutectic bond is between a first bonding metal on the bonding electrode and a second bonding metal on the MEMS wafer. A sensing electrode is positioned adjacent to the bump stop electrode and the bonding electrode. A sensing gap is positioned between the sensing electrode and the device layer, wherein the sensing gap is greater than a bump stop gap positioned between the bump stop electrode and the device layer.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: September 15, 2020
    Assignee: InvenSense, Inc.
    Inventors: Daesung Lee, Jeff Chunchieh Huang
  • Patent number: 10763218
    Abstract: An electrical device includes at least one electrical component arranged on a carrier substrate and sidewalls of an electromagnetic shielding encapsulation arranged on the carrier substrate. The sidewalls of the electromagnetic shielding encapsulation laterally surround the at least one electrical component. Further, the electrical device includes a heat sink mounted to the sidewalls of the electromagnetic shielding encapsulation. The heat sink forms a cap of the electromagnetic shielding encapsulation and the heat sink includes surface-enlarging structures at a front side of the heat sink.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Sruti Chigullapalli, Leslie Fitch, Boping Wu
  • Patent number: 10763329
    Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, a channel region, a pair of source/drain regions and a threshold voltage adjusting region. The gate electrode is over the semiconductor substrate. The channel region is between the semiconductor substrate and the gate electrode. The channel region includes a pair of first sides opposing to each other in a channel length direction, and a pair of second sides opposing to each other in a channel width direction. The source/drain regions are adjacent to the pair of first sides of the channel region in the channel length direction. The threshold voltage adjusting region covers the pair of second sides of the channel region in the channel width direction, and exposing the pair of first sides of the channel region in the channel length direction.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
  • Patent number: 10763163
    Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su-jeong Park, Dong-chan Lim, Kwang-jin Moon, Ju-bin Seo, Ju-il Choi, Atsushi Fujisaki
  • Patent number: 10756256
    Abstract: A magnetoresistive random access memory and a method for manufacturing the same are provided, with which a stress layer covers a part of the protective layer along a direction of a current in the spin-orbit coupling layer, so that a stress is generated on the part of the magnetic layer locally due to the stress layer, thus a lateral asymmetric structure is formed in a direction perpendicular to the current source. In a case that a current is supplied to the spin-orbit coupling layer, the spin-orbit coupling effect in the magnetic layer is asymmetric due to the stress on the part of the magnetic layer, thereby realizing a deterministic switching of the magnetic moment under the function of the stress.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: August 25, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Meiyin Yang, Jun Luo, Tengzhi Yang, Jing Xu
  • Patent number: 10741694
    Abstract: In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm2 and lower than or equal to 0.5 W/cm2 is supplied to an electrode provided in the treatment chamber.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: August 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenichi Okazaki, Toshinari Sasaki, Shuhei Yokoyama, Takashi Hamochi
  • Patent number: 10734308
    Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate and at least one through silicon via. The through silicon via includes a conductive plug, a first insulation layer, and a diffusion barrier layer. The conductive plug penetrates through the semiconductor substrate. The first insulation layer surrounds the conductive plug. The diffusion barrier layer is disposed between the conductive plug and the first insulation layer, and is utilized to prevent out-diffusion of dopant impurities from the conductive plug to the semiconductor substrate.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: August 4, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 10734053
    Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The conductive member includes a first layer. The first layer includes at least one selected from the group consisting of HfN having a NaCl structure, HfN having a fcc structure, and HfC having a NaCl structure. The first magnetic layer is separated from the first layer in a first direction. The second magnetic layer is provided between the first layer and the first magnetic layer. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: August 4, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mizue Ishikawa, Yushi Kato, Soichi Oikawa, Hiroaki Yoda
  • Patent number: 10734562
    Abstract: Some embodiments provide a substrate terminal board in which the number of components is reduced by utilizing a conductor board per se constituting the substrate terminal board while ensuring heat dissipation, and which has a simple structure. Heat-dissipation fins can be cut and raised at a plurality of positions around element mounting portions of an upper-substrate conductor board, thus providing heat-dissipation fins and heat-dissipation openings. The upper-substrate conductor board can be coated with a paint film to form an upper substrate. A lower-substrate conductor board can be coated with the paint film to form a lower substrate. In a pressing/heating process, the lower substrate and the upper substrate can overlap each other and be vertically pressed while the lower substrate and the upper substrate are heated to completely cure the paint film, thereby causing the paint film on the lower substrate and the paint film on the upper substrate to adhere to each other.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: August 4, 2020
    Assignees: SUNCALL CORPORATION, STANLEY ELECTRIC CO., LTD.
    Inventors: Masaya Nakagawa, Shojiro Wakabayashi, Mamoru Yuasa, Toshifumi Watanabe
  • Patent number: 10734479
    Abstract: A FinFET having an asymmetric threshold voltage distribution is provided by modifying a portion of the channel region of a semiconductor fin that is nearest to the drain side with an epitaxial semiconductor material layer. In some embodiments, the channel region of the semiconductor fin nearest to the drain side is trimmed prior to forming the epitaxial semiconductor material layer.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Choonghyun Lee, Takashi Ando, Jingyun Zhang, Pouya Hashemi
  • Patent number: 10727231
    Abstract: A heterogeneously integrated semiconductor device includes a substrate comprising a first material; a recess formed within the substrate and having a bottom portion with a first width, a top portion with a second width and a middle portion with a third width larger than the first width and the second width; and a first semiconductor layer filled in the bottom portion and including a second material different from the first material.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: July 28, 2020
    Assignees: National Applied Research Laboratories, EPISTAR Corporation
    Inventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
  • Patent number: 10727205
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • Patent number: 10727130
    Abstract: A semiconductor device and a fabrication method are provided. The fabrication method includes providing a base substrate including a core region having a first gate structure formed thereon, and an edge region having a second gate structure formed thereon; forming a source/drain doped layer, in the core region of the base substrate on both sides of the first gate structure, and in the edge region of the base substrate on both sides of the second gate structure, respectively, the source/drain doped layer including first ions; and doping the second ions in the source/drain doped layer in the edge region, the second ions having a conductivity type opposite to the first ions.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 28, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10714569
    Abstract: Strained nanosheet field effect transistors (FETs) using a phase change material are described herein. In some embodiments, a semiconductor device can comprise alternating layers of a channel material and a phase change material to produce strained nanosheet field effect transistors, wherein the layers of the phase change material cause a strain in the layers of the channel material. The phase change material comprises germanium antimony telluride. The germanium antimony telluride crystallizes into a crystalline germanium antimony telluride based on annealing above 300 degrees Celsius and a volume of the crystalline germanium antimony telluride is reduced up to six percent relative to an initial volume the germanium antimony telluride to cause the strain in the layers of the channel material. The semiconductor device can also comprise source and drain epitaxial growths on both ends of the layers of the channel material that lock the strain in the layers of the channel material.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: July 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dexin Kong, Kangguo Cheng, Juntao Li, Zhenxing Bi
  • Patent number: 10707300
    Abstract: A semiconductor device having a trench gate structure is provided. A semiconductor device is provided, including: a first-conductivity-type drift region provided in a semiconductor substrate; a first-conductivity-type accumulation region provided above the drift region and having a higher doping concentration than the drift region; a second-conductivity-type base region provided above the accumulation region; and an electric-field relaxation layer provided between the accumulation region and the base region and having a lower doping concentration than the accumulation region. The electric-field relaxation layer may include a first-conductivity-type region including a region having a same doping concentration as the drift region.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: July 7, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yosuke Sakurai, Yuichi Onozawa, Akio Nakagawa