Abstract: Provided are a display panel, a manufacturing method thereof, and a display device. The display panel includes an alignment mark region arranged within a flat region of a peripheral region of the display panel. The peripheral region is a region of the display panel other than an active area of the display panel. An alignment mark pattern is arranged within the alignment mark region, and/or at least one film layer within the alignment mark region is hollowed out.

Abstract: A display panel and a display device are provided. The display panel includes a photosensitive array layer including a plurality of photosensitive units arranged in an array, a light-emitting function layer, and a color resist layer. The light-emitting function layer is disposed between the color resist layer and the photosensitive array layer. The color resist layer includes a first light-shielding layer and a plurality of first color resist units. The first light-shielding layer contains a plurality of first openings and a plurality of second openings. A first opening of the plurality of first openings corresponds to a photosensitive unit of the plurality of photosensitive units, and a first color resist unit of the plurality of first color resist units at least covers a second opening of the plurality of second openings. At least one of the plurality of second openings is connected with the first opening.

Abstract: A three-dimensional flash memory including an intermediate wiring layer and a method of manufacturing the same are disclosed.

Abstract: Provided are an optoelectronic apparatus including an on-chip optoelectronic diode capable of receiving and emitting light, and a method of manufacturing the same.

Abstract: A deep UV light emitting diode includes a substrate, an n-type semiconductor layer located on the substrate, a mesa disposed on the n-type semiconductor layer, and including an active layer and a p-type semiconductor layer, an n-ohmic contact layer in contact with the n-type semiconductor layer, a p-ohmic contact layer in contact with the p-type semiconductor layer, an n-bump electrically connected to the n-ohmic contact layer, and a p-bump electrically connected to the p-ohmic contact layer. The mesa includes a plurality of vias exposing a first conductivity type semiconductor layer.

Abstract: A light-emitting device includes: an anode; a cathode; a light-emitting layer between the anode and the cathode; and a hole transport layer between the anode and the light-emitting layer, the hole transport layer containing carbon and a metal oxide in a prescribed, adjusted ratio.

Abstract: A display device includes a plurality of pixels, each of the plurality of pixels including an emission area, a first electrode and a second electrode that are disposed in the emission area to be spaced apart from each other, and a plurality of light emitting elements that are electrically connected between the first and second electrodes, and a bank disposed between the emission area of each of the plurality of pixels to enclose the emission area. The first electrode includes a first electrode part disposed in the emission area to be adjacent to a first side of the second electrode, a second electrode part disposed in the emission area to be adjacent to a second side of the second electrode, and a third electrode part electrically connecting the first and second electrode parts and disposed in the emission area to be adjacent to a third side of the second electrode.

Abstract: The present application discloses a method for preparing a semiconductor device including an electronic fuse control circuit. The method includes providing a chip including an electronic fuse control circuit, wherein the electronic fuse control circuit includes a program voltage pad, a fuse element, a latch, a plurality of resistor selection pads, and a plurality of bonding option units. The method further includes providing a substrate including a first voltage bonding pad and a plurality of second voltage bonding pads, disposing the chip on the substrate, bonding the first voltage bonding pad to the program voltage pad, and bonding at least one of the plurality of second voltage bonding pads to at least one of the plurality of resistor selection pads.

Abstract: A semiconductor device includes a gate electrode, first and second passivation layers, first and second field plates. The gate electrode is disposed above nitride-based semiconductor layers. The first passivation layer covers the gate electrode. The first field plate is disposed on the first passivation layer. The first passivation layer has a first portion covered with the first field plate and a second portion free from coverage of the first field plate. The second passivation layer covers the first field plate. The second field plate is disposed over the second passivation layer. The second passivation has a first portion covered with the second field plate and a second portion is free from coverage of the second field plate. A thickness difference between the first and second portions of the first passivation layer is less than a thickness difference between the first and second portions of the second passivation layer.

Abstract: Embodiments of three-dimensional semiconductor devices and fabrication methods are disclosed. The method includes forming a first and a second memory chips and a microprocessor chip. The method also includes bonding a first interconnect layer of the first memory chip with a second interconnect layer of the second memory chip, such that one or more first memory cells of the first memory chip are electrically connected with one or more second memory cells of the second memory chip through interconnect structures of the first and second interconnect layers. The method further includes bonding a third interconnect layer of the microprocessor chip with a substrate of the second memory chip, such that the one or more microprocessor devices of the microprocessor chip are electrically connected with one or more second memory cell of the second memory chip through interconnect structures of the second and third interconnect layers.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: A solid-state imaging element including: a photoelectric conversion layer, a first electrode and a second electrode opposed to each other with the photoelectric conversion layer interposed therebetween, a semiconductor layer provided between the first electrode and the photoelectric conversion layer, an accumulation electrode opposed to the photoelectric conversion layer with the semiconductor layer interposed therebetween, an insulating film provided between the accumulation electrode and the semiconductor layer, and a barrier layer provided between the semiconductor layer and the photoelectric conversion layer.

Abstract: A display panel having a plurality of subpixels is provided. The display panel includes a black matrix layer; a black adhesive layer on the black matrix layer; and a cover an a side of the black adhesive layer away from the black matrix layer. The black adhesive layer extends substantially throughout an entirety of a display region of the display panel, including a subpixel region and an inter-subpixel region. The black adhesive layer includes an optically clear adhesive and particles distributed throughout the optically clear adhesive. Light transmittance of the black adhesive layer is in a range of 40% to 80%.

Abstract: A memory device and a method for manufacturing the same, and an electronic apparatus including the memory device are provided. The memory device may include: a substrate (1001); an electrode structure on the substrate (1001), in which the electrode structure includes a plurality of first electrode layers and a plurality of second electrode layers that are alternately stacked; a plurality of vertical active regions penetrating the electrode structure; a first gate dielectric layer and a second gate dielectric layer, in which the first gate dielectric layer is between the vertical active region and each first electrode layer of the electrode structure, and the second gate dielectric layer is between the vertical active region and each second electrode layer of the electrode structure, each of the first gate dielectric layer and the second gate dielectric layer constitutes a data memory structure.

Abstract: We disclose herein a hetero-structure comprising: a curved material; at least one layer of a first material rolled around the curved material; at least one intermediate layer rolled on the at least one layer of the first material; and at least one layer of a second material rolled around the at least one intermediate layer.

Abstract: A display substrate, a display panel, and a display apparatus. The display substrate includes: a first display area including a plurality of first sub-pixels; a second display area including a plurality of second sub-pixels; a shielding layer provided in the second display area; a first signal line configured to provide a control signal to the first sub-pixels, wherein the first signal line extends from the first display area through the second display area, and a portion of the first signal line located in the second display area is provided above the shielding layer; and a pixel circuit provided below the shielding layer and configured to drive the second sub-pixels; wherein the shielding layer is configured to shield an electric field between the portion of the first signal line located in the second display area and the pixel circuit.

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

Abstract: Disclosed in embodiments of the present disclosure are a display panel and a manufacturing method therefor, and a display apparatus. The display panel includes: a base substrate; an organic functional film layer provided on the base substrate; an insulating layer provided on the organic functional film layer, a plurality of dents distributed at intervals are provided on one side of the insulating layer distant from the organic functional film layer; and an amorphous silicon solar cell film layer provided at one side of the insulating layer distant from the organic functional film layer, the amorphous silicon solar cell film layer has the same morphology as the surface of the insulating layer where the dents are provided.

Abstract: A method for producing a printable ink for an electronic component in which a transition metal-containing pseudohalide or chalcogenide is first complexed by a pyridine-like or thiol-like solvent, in order to improve or achieve solubility. Subsequently, by filtering and mixing with at least one solvent a printable ink is produced. The printable ink can be used to produce hole transport or electron blocking layers of electronic components.

Abstract: A display device includes a pixel array including a plurality of pixels, and a sensor disposed below the pixel array that includes a first region having a low resolution and overlapping the sensor, and a second region having a high resolution and disposed adjacent to the first region, the first region includes a plurality of first pixels having a first structure, the second region includes a plurality of second pixels having a second structure different from the first structure, and a light-emitting region of each of the first pixels is wider than a light-emitting region of each of the second pixels.