Abstract: A light emitting display panel includes a substrate, a pixel driving circuit disposed on the substrate, a planarization layer disposed on the pixel driving circuit, a pixel driving electrode disposed on the planarization layer and electrically connected to the pixel driving circuit, a light emitting layer disposed on the pixel driving electrode, and a common electrode disposed on the light emitting layer. The pixel driving electrode includes a plurality of first electrodes apart from one another and a second electrode covering the first electrodes, and at least one of the second electrode or the plurality of first electrodes is connected to the pixel driving circuit.

Abstract: An aspect comprising an optical sensor is disclosed. The optical sensor comprises stacked layers comprising: a window layer configured to allow the passage of photons; a sensing layer configured to generate charges upon impinging of the photons through the window layer; and a bottom electrode layer comprising at least one bottom electrode for receiving charges generated in the sensing layer. The sensing layer is sandwiched between the window layer and the bottom electrode layer. The at least one bottom electrode of the bottom electrode layer comprises conductive material with reflectivity higher than 0.7 to reflect back received photons into the sensing layer; and the at least one bottom electrode is obtained by semiconductor device fabrication techniques.

Abstract: This disclosure provides a perovskite light-emitting diode with an adjustable light field, including a glass layer, an anode, a hole transport layer, an emission layer, an electron transport layer and a cathode in sequence from top to bottom. The electron transport layer is provided with a periodic nano-grating structure.

Abstract: An display device may include a substrate including an active area and an inactive area surrounding the active area, a plurality of thin film transistors disposed in the active area, each of the thin film transistor including a semiconductor layer and a first electrode, a light emitting elements disposed in the active area, each of the light emitting element including an anode electrode and an organic light emitting layer, a connection area and a peripheral area disposed in the inactive area, and a first reflective electrode disposed in the connection area.

Abstract: A light-emitting device includes: a first electrode; a second electrode facing the first electrode; and an interlayer disposed between the first electrode and the second electrode and including an emission layer; wherein the interlayer further includes: a layer A including an oxide of an inorganic compound; a layer B adjacent to an upper portion of the layer A and including an oxide of an inorganic compound; and a layer C adjacent to a lower portion of the layer A and including an oxide of an inorganic compound, and relationships between a refractive index a of the layer A, a refractive index b of the layer B, and a refractive index c of the layer C satisfy the Equations (1) and (2) defined herein.

Abstract: A semiconductor component includes a semiconductor component, including: a merged PiN Schottky (MPS) diode structure in a SiC semiconductor body having a drift zone of a first conductivity type; an injection region of a second conductivity type adjoining a first surface of the SiC semiconductor body; a contact structure at the first surface, the contact structure forming a Schottky contact with the drift zone and electrically contacting the injection region; and a zone of the first conductivity type formed between the injection region and a second surface of the SiC semiconductor body, the second surface being situated opposite the first surface. The zone is at a maximal distance of 1 ?m from the injection region of the second conductivity type.

Abstract: A display device includes signal lines and pixels connected thereto. A first pixel includes a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode, a first source region, and a second drain region facing the first source region, with the first channel region interposed between the first source region and the second drain region. A third transistor includes a third gate electrode, a third channel region overlapping the third gate electrode, a third drain region connected to the first gate electrode, and a third source region facing the third drain region with the third channel region interposed between the third source region and the third drain region. A shielding part overlaps a boundary between the third source region and the third channel region and does not overlap a boundary between the third drain region and the third channel region.

Abstract: An array substrate, a display panel and a display device are provided. The display substrate includes: a substrate, a planarization layer, a middle layer and a first electrode layer. The substrate includes a first area and a second area. The planarization layer is located on the substrate and covers the first area and the second area. The middle layer is located on the planarization layer and includes at least one transparent conductive sub-layer and at least one isolation protective sub-layer. A projection of the transparent conductive sub-layer on the substrate is located in the first area, and a projection of the isolation protective sub-layer on the substrate is located in the second area. The first electrode layer is located on the middle layer and includes at least one first electrode located on the transparent conductive sub-layer and at least one second electrode located on the isolation protective sub-layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and an adjacent second fin structure protruding from the semiconductor substrate and an isolation structure formed in the semiconductor substrate and in direct contact with the first fin structure and the second fin structure. The first fin structure and the second fin structure each include a first portion protruding above a top surface of the isolation structure, a second portion in direct contact with a bottom surface of the first portion, and a third portion extending from a bottom of the second portion. A top width of the third portion is different than a bottom width of the third portion and a bottom width of the second portion.

Abstract: A light emitting element includes a first semiconductor layer; an active layer on the first semiconductor layer; a second semiconductor layer on the active layer; an insulating film surrounding an outer peripheral surface of each of the first semiconductor layer, the active layer and the second semiconductor layer; and a polymer film including a polymer chain and on at least a portion of a surface of the insulating film.

Abstract: Provided herein are semiconductor structures that include germanium and have a germanium nitride layer on the surface, as well as methods of forming the same. The described structures include nanowires and fins. Methods of the disclosure include metal-organic chemical vapor deposition with a germanium precursor. The described methods also include using a N2H4 vapor.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.

Abstract: A light emitting device including a blue light emitting portion configured to emit blue light, a green light emitting portion configured to emit green light, a red light emitting portion configured to emit red light, in which the blue light emitting portion include a first near-UV light emitting diode chip and a first wavelength conversion portion for wavelength conversion of near-UV light emitted from the first near-UV light emitting diode chip, blue light emitted from the blue light emitting portion includes a first peak wavelength in a wavelength band corresponding to near-UV light and a second peak wavelength in a wavelength band corresponding to blue light, and an intensity of the first peak wavelength is in a range of 0% to 20% of intensity of the second peak wavelength.

Abstract: A display panel includes a base substrate; and a light-emitting device layer, disposed on the base substrate and including sub-pixels. A sub-pixel includes light-emitting regions and a non-light-emitting regions located between adjacent light-emitting regions. The display panel includes a light-shielding layer, disposed on the side of the light-emitting device layer away from the base substrate and including a light-shielding structure located in the non-light-emitting region; and a polarizer, disposed on the side of the light-shielding layer away from the base substrate and having an absorption axis in a first direction. In each sub-pixel, along the first direction, the minimum distance between the boundary of the light-emitting region and the light-shielding structure is a first distance B; along a second direction intersected with the first direction, the minimum distance between the boundary of the light-emitting region and the light-shielding structure is a second distance A; and B>A.

Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.

Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.

Abstract: A display device includes a first substrate and a second substrate at which a display area for displaying an image and a non-display area surrounding the display area are provided; a light-emitting diode in the display area on an inner surface of the first substrate and including an anode electrode, a light-emitting layer and a cathode electrode; and a piezoelectric element in the display area on an inner surface of the second substrate and including a first electrode, a piezoelectric layer and a second electrode, wherein the piezoelectric layer includes dichroic dyes.

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

Abstract: In an example, the present invention provides a method of manufacturing a solar module. The method includes providing a substrate member having a surface region, the surface region comprising a spatial region, a first end strip comprising a first edge region and a first interior region, the first interior region comprising a first bus bar, a plurality of strips, a second end strip comprising a second edge region and a second interior region, the second edge region comprising a second bus bar, the first end strip, the plurality of strips, and the second end strip arranged in parallel to each other and occupying the spatial region such that the first end strip, the second end strip, and the plurality of strips consists of a total number of five (5) strips. The method includes separating each of the plurality of strips, arranging the plurality of strips in a string configuration, and using the string in the solar module.

Abstract: A display panel includes a plurality of light-emitting elements. Light emitted from a first light-emitting element has a CIE 1931 chromaticity coordinate x of greater than 0.680 and less than or equal to 0.720 and a CIE 1931 chromaticity coordinate y of greater than or equal to 0.260 and less than or equal to 0.320. Light emitted from a second light-emitting element has a CIE 1931 chromaticity coordinate x of greater than or equal to 0.130 and less than or equal to 0.250 and a CIE 1931 chromaticity coordinate y of greater than 0.710 and less than or equal to 0.810. Light emitted from a third light-emitting element has a CIE 1931 chromaticity coordinate x of greater than or equal to 0.120 and less than or equal to 0.170 and a CIE 1931 chromaticity coordinate y of greater than or equal to 0.020 and less than 0.060.