Patents Examined by Daniel P Shook
  • Patent number: 10868013
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Patent number: 10867855
    Abstract: One or more embodiments are directed to establishing electrical connections through silicon wafers with low resistance and high density, while at the same time maintaining processability for further fabrication. Such connections through silicon wafers enable low resistance connections from the top side of a silicon wafer to the bottom side of the silicon wafer.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 15, 2020
    Assignee: Honeywell International Inc.
    Inventors: Robert E. Higashi, Son T. Lu, Elenita Chanhvongsak
  • Patent number: 10861809
    Abstract: A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 10861812
    Abstract: An electronic apparatus includes first and second packages. The first package includes a first semiconductor chip between opposing first and second surfaces of the first package, a plurality of terminals on the first semiconductor chip facing a first direction that is perpendicular to the first and second surface, the terminals including first input/output terminals and a second input/output terminal, and a plurality of bumps that are electrically connected to the plurality of first input/output terminals at positions that are directly below the first semiconductor chip in the first direction. The second package includes a second semiconductor chip provided on the second surface of the first package, a wire that electrically connects the second semiconductor chip to a conductor that is electrically connected to the second input/output terminal, and coating resin that covers the second surface of the first package, the second semiconductor chip and the wire.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: December 8, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Hideo Aoki
  • Patent number: 10854820
    Abstract: The present disclosure provides a blue organic electroluminescent device comprising: a substrate; an anode layer disposed on the substrate; a light emitting layer disposed on the anode layer, the light emitting layer being formed from a blue organic fluorescent material and a hole-type organic host material, wherein the blue organic fluorescent material is 8.0% to 25.0% by mass of the hole-type organic host material; and a cathode layer disposed on the light emitting layer.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: December 1, 2020
    Assignee: Changchun Institute of Applied Chemistry Chinese Academy of Sciences
    Inventors: Liang Zhou, Hongjie Zhang, Xuesen Zhao
  • Patent number: 10854745
    Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: December 1, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Dinesh Maheshwari, Yuniarto Widjaja
  • Patent number: 10847465
    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. At least two metal elements are formed in the dielectric layer, wherein an air gap is between adjacent two of the metal elements. A cap layer is disposed over the substrate, wherein a portion of the cap layer above the adjacent two of the metal elements has a hydrophilic surface. An inter-layer dielectric layer is disposed on the cap layer. The inter-layer dielectric layer seals the air gap between the two metal elements. The air gap remains and extends higher than a top surface of the metal elements.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: November 24, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, San-Fu Lin
  • Patent number: 10839909
    Abstract: A shared floating gate device, the device including an nFET, a pFET including a different material than that of the nFET, and a floating gate.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tak Ning, Jeng-Bang Yau
  • Patent number: 10833287
    Abstract: A flexible display device includes: an organic light emitting layer for emitting light; a cathode electrode layer disposed on the organic light emitting layer; and a cavity region located between a plane where the cathode electrode layer is located and the organic light emitting layer.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: November 10, 2020
    Assignee: Kunshan New Flat Panel Display Technology Center Co., Ltd.
    Inventors: Jiawei Li, Weiwei Li, Kun Hu
  • Patent number: 10833006
    Abstract: A semiconductor device includes a substrate, a first electrode provided apart from the surface of the substrate in a first direction intersecting the surface of the substrate, a second electrode extending completely through the substrate in the first direction and connected to the first electrode at one end in the first direction, a first structure covering a side surface of the second electrode, and an insulating film provided between the second electrode and the first structure. The second electrode includes first atoms, and the first structure includes second atoms. A diffusion coefficient of the second atoms in the insulating film is smaller than a diffusion coefficient of the first atoms in the insulating film.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: November 10, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiromasa Yoshimori, Masayuki Ako
  • Patent number: 10811430
    Abstract: Three-dimensional semiconductor memory devices are provided. The devices may include a semiconductor layer and electrode structures on the semiconductor layer. The electrode structures may include a first electrode structure including a first electrode portion and a first pad portion and a second electrode structure including a second electrode portion and a second pad portion. Each of the first and second electrode portions has a first width, each of the first and second pad portions has a second width, and the second width may be less than the first width. The first and second electrode portions may be spaced apart from each other by a first distance, and the first and second pad portions may be spaced apart from each other by a second distance that may be greater than the first distance.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seokcheon Baek, Kwang-Soo Kim
  • Patent number: 10811596
    Abstract: A MRAM cell includes a magnetic tunnel junction containing a reference layer having a fixed magnetization direction, a free layer, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer, a spin torque oscillator stack, and a first nonmagnetic spacer layer located between the free layer and the a spin torque oscillator stack.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 20, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Quang Le, Zhanjie Li, Zhigang Bai, Paul Vanderheijden, Michael Ho
  • Patent number: 10811399
    Abstract: An optical sensing chip packaging structure includes a substrate, an optical sensing member, a light emitting member and a transparent cover plate. The substrate has a recess; the optical sensing member is positioned in the recess, and is electrically connected to the substrate. The light emitting member is positioned in the recess, and is electrically connected to the substrate or the optical sensing member. The transparent cover plate is positioned on the substrate, and covers the optical sensing member and the light emitting member.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 20, 2020
    Assignee: TAIWAN ELECTRONIC PACKAGING CO., LTD.
    Inventor: Cherng-Chiao Wu
  • Patent number: 10804500
    Abstract: The present application relates to an optical filter and an organic light-emitting display device. The optical filter of the present application has excellent omnidirectional antireflection performance and color characteristics on the side as well as the front, and the optical filter can be applied to an organic light-emitting device to improve visibility.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: October 13, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Sun Kug Kim, Hyuk Yoon, Moon Soo Park, Jong Hyun Jung
  • Patent number: 10797072
    Abstract: A semiconductor device according to an embodiment includes an N-well region, a first gate electrode, a columnar epitaxial layer, and a first contact. The N-well region includes two P-type impurity diffusion regions. The first gate electrode is provided above the N-well region between the two P-type impurity diffusion regions. The first gate electrode are opposed to the N-well region via a gate insulating film. The columnar epitaxial layer is provided on the P-type impurity diffusion region. The epitaxial layer includes a first semiconductor layer including P-type impurities. The first contact is provided on the first semiconductor layer of the epitaxial layer.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: October 6, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takuya Inatsuka, Taichi Iwasaki, Osamu Matsuura
  • Patent number: 10797167
    Abstract: In at least one general aspect, a method can include forming a plurality of first active pillars and a plurality of edge pillars in a first semiconductor layer including an active region and a termination region, and forming a second semiconductor layer on the first semiconductor layer. The method can include forming a plurality of second active pillars and a plurality of preliminary charge balance layers in the second semiconductor layer, and annealing the first and second semiconductor layers such that the plurality of first active pillars and the plurality of second active pillars are connected by diffusing impurities implanted into the plurality of first active pillars and the plurality of second active pillars.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: October 6, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Kwang-won Lee, Hye-min Kang, Jae-gil Lee
  • Patent number: 10790184
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region and a second well region that have different conductivity types and are adjacent to each other. A first fin structure protrudes from the semiconductor substrate and is formed in the first well region. A second fin structure protrudes from the semiconductor substrate and is formed in the second well region and adjacent to the first fin structure. A first multi-step isolation structure that includes a first isolation portion is formed between the first fin structure and the second fin structure. A second isolation portion extends from the bottom surface of the first isolation portion. The second isolation portion has a top width that is narrower than the bottom width of the first isolation portion.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Chun Lin, Tien-Shao Chuang, Kuang-Cheng Tai, Chun-Hung Chen, Chih-Hung Hsieh, Kuo-Hua Pan, Jhon-Jhy Liaw
  • Patent number: 10790248
    Abstract: Provided are a three-dimensional integrated circuit (3DIC) and a method of manufacturing the same. The 3DIC includes a first wafer, a second wafer, and a hybrid bonding structure. The second wafer is bonded to the first wafer by the hybrid bonding structure. The hybrid bonding structure includes a blocking layer between a hybrid bonding dielectric layer and a hybrid bonding metal layer.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 29, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hung Chen, Ming-Tse Lin
  • Patent number: 10784196
    Abstract: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via parallel to the first surface of the substrate, wherein the first conductive line includes a second surface at least partially interfaced with the conductive via, the second surface of the first conductive line includes a first end, a second end opposite to the first end and a first central axis passing through the first end and the second end, the cross section of the conductive via includes a second central axis parallel to the first central axis and a third central axis orthogonal to the second central axis.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Ta Lu, Chi-Ming Tsai
  • Patent number: 10784237
    Abstract: In a method for fabricating an emissive display, a package substrate with a top thereof having a plurality of wells is firstly provided. The well has a first electrode region and a second electrode region at different heights. The package substrate sinks in a suspension. Then, a plurality of light-emitting diodes sinks in the suspension. The light-emitting diode has a plane and a curved surface. Finally, the suspension horizontally jets such that the suspension flows across the plane and the curved surface of the light-emitting diode at different velocities. According to the different velocities, the suspension respectively embeds all the light-emitting diodes into all the wells. Each of the plurality of light-emitting diodes are respectively electrically connected to the first electrode region and the second electrode region of a corresponding one of the plurality of wells, thereby forming an emissive display.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: September 22, 2020
    Assignees: INTERFACE TECHNOLOGY (CHENGDU) CO., LTD., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventor: Chin-Feng Chung