Patents Examined by Daniel P Shook
  • Patent number: 10431553
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface, which includes an element forming region and an element isolation region, and a second surface opposite to the first surface, a semiconductor element formed on the semiconductor substrate in the element forming region, an insulator formed on the semiconductor substrate in the element isolation region, a first wiring layer formed on the first surface of the semiconductor substrate, the first wiring layer being connected to the semiconductor element, an alignment mark formed on the semiconductor substrate in the element isolation region, the entire alignment mark overlapping with the insulator in a plan view of the semiconductor device, and a second wiring layer formed on the second surface of the semiconductor substrate.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: October 1, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Azusa Ozawa
  • Patent number: 10424637
    Abstract: A method of manufacturing a semiconductor device that includes a semiconductor layer of a first conductivity type, and a parallel pn layer formed on the semiconductor layer, the pn layer having first semiconductor regions of the first conductivity type and second semiconductor regions of a second conductivity type, the first and second regions being alternately arranged parallel to a surface of the semiconductor layer. In one embodiment, the method includes repeatedly performing the following steps to stack the epitaxial growth layers on the semiconductor layer to form the pn layer: forming an epitaxial growth layer of the first conductivity type or non-doped, the epitaxial growth layer having an impurity concentration lower than that of the semiconductor layer, ion implanting a first-conductivity-type impurity into the epitaxial growth layer, selectively ion implanting a second-conductivity-type impurity into the epitaxial growth layer and ion implanting a group 18 element into the epitaxial growth layer.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: September 24, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shuhei Tatemichi, Shunji Takenoiri
  • Patent number: 10424753
    Abstract: The invention relates to production method of PEDOT:PSS film which comprises the steps of preparing substrate, preparing the mixture of boric acid doped PEDOT:PSS prepare on the substrate surface.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: September 24, 2019
    Inventors: Orhan Icelli, Serap Gunes, Sureyya Aydin Yuksel, Serco Serkis Yesilkaya, Ozlem Yagci
  • Patent number: 10421721
    Abstract: The present specification relates to a hetero-cyclic compound and an organic light emitting device including the same.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: September 24, 2019
    Assignee: LG Chem, Ltd.
    Inventors: Yongbum Cha, Jin Joo Kim, Sung Kil Hong, Sang Duk Suh
  • Patent number: 10424610
    Abstract: A capacitor, an image sensor circuit and fabricating methods are provided. The method includes providing a base substrate including a trench region and a body region adjacent to the trench region. The method also includes forming a first trench structure and a second trench structure on the first trench structure, in the base substrate in the trench region. In addition, the method includes forming a dielectric layer on a sidewall surface and a bottom surface of the first trench structure and an electrode layer on the dielectric layer in the first trench structure. Further, the method includes forming an isolation layer filling the second trench structure.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: September 24, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Xin Liang, Chong Wang
  • Patent number: 10418367
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.
    Type: Grant
    Filed: July 8, 2018
    Date of Patent: September 17, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Ching Chang, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10418445
    Abstract: In a vertical MOSFET having a trench gate structure, a lifetime killer region is provided in a p-type epitaxial layer formed by epitaxial growth. The lifetime killer region includes an electron lifetime killer that causes electrons entering the lifetime killer region to recombine and become extinct. As a result, the lifetime killer region decreases the electrons generated at the pn interface of the p-type epitaxial layer and an n-type drift layer and enables a configuration in which electrons are not delivered to the p-type epitaxial layer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: September 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Mina Ryo, Takeshi Tawara, Masaki Miyazato, Masaaki Miyajima
  • Patent number: 10410945
    Abstract: Provided is a semiconductor device with high reliability. In order to solve the above problems, according to the present invention, the semiconductor device includes a heat dissipating substrate, an insulating substrate arranged on the heat dissipating substrate and having a wiring layer, a plurality of semiconductor elements arranged on the insulating substrate, a conductive block electrically connected to a front surface electrode of the semiconductor element, and a terminal electrode, in which the conductive block has a convex portion, and the convex portion is bonded to the insulating substrate.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: September 10, 2019
    Assignee: HITACHI, LTD.
    Inventor: Akitoyo Konno
  • Patent number: 10411058
    Abstract: A semiconductor apparatus includes a silicon layer including first and second semiconductor regions; an insulator film, on the silicon layer, having first and second holes positioned on the first and second semiconductor regions; a first metal portion containing a first metal element in the first hole; a first conductor portion containing a second metal element between the first metal portion and the first semiconductor region; a first silicide region containing the second metal element between the first conductor portion and the first semiconductor region; a second metal portion containing the first metal element in the second hole; a second conductor portion containing the second metal element between the second metal portion and the second semiconductor region; and a second silicide region containing a third metal element between the second conductor portion and the second semiconductor region, wherein the first conductor portion thickness is greater than the second conductor portion thickness.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: September 10, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tsutomu Tange, Yukinobu Suzuki, Aiko Kato, Koji Hara, Takehito Okabe
  • Patent number: 10410926
    Abstract: The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: September 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, Pouya Hashemi
  • Patent number: 10403557
    Abstract: A semiconductor device comprising: a semiconductor component; a diamond heat spreader; and a metal bond, wherein the semiconductor component is bonded to the diamond heat spreader via the metal bond, wherein the metal bond comprises a layer of chromium bonded to the diamond heat spreader and a further metal layer disposed between the layer of chromium and the semiconductor component, and wherein the semiconductor component is configured to operate at an areal power density of at least 1 kW/cm2 and/or a linear power density of at least 1 W/mm.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: September 3, 2019
    Assignee: ELEMENT SIX TECHNOLOGIES LTD
    Inventors: Julian Anaya Calvo, Martin Hermann Hans Kuball, Julian James Sargood Ellis, Daniel James Twitchen
  • Patent number: 10396006
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: August 27, 2019
    Assignee: NXP USA, Inc.
    Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos, Jaynal A. Molla
  • Patent number: 10388638
    Abstract: Provided is a light-emitting diode (LED) module, LED panel and LED screen. The LED module includes a composite layer, at least one LED chipset with an LED chip, at least one driver integrated circuit (IC); the composite layer includes a substrate arranged at the front side; the LED chip and the driver IC are installed at the front side of the composite layer, the cathode of the LED chip is connected to the driver IC by golden wire bonding; blind holes are arranged at the front side of the composite layer, the anode of the LED chip is connected to the positive electrode inside the composite layer through one of the blind holes; the wire coming from the VDD pin of the driver IC is connected to the positive electrode inside the composite layer through at least one of the blind holes; the wire coming from the GND pin of the driver IC is connected to the negative electrode inside the composite layer through one of the blind holes; the at least one driver IC is connected with each other through a signal line.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: August 20, 2019
    Inventor: Shuling Li
  • Patent number: 10388526
    Abstract: Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: August 20, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Thomas Neyer
  • Patent number: 10373889
    Abstract: In an electronic device including an electronic component, a sealing resin body, a first member having at least a portion located in the sealing resin body, and a second member connected to the first member via a solder in the sealing resin body, the first member includes a base material formed of a metal material and a coated film at least on a surface of the base material which is adjacent to a back surface of the first member opposite to a facing surface of the first member facing the second member. The coated film includes a metal thin film on a surface of the base material and an uneven oxide film on the metal thin film and made of an oxide of a same metal as a main component of the metal thin film.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: August 6, 2019
    Assignee: DENSO CORPORATION
    Inventors: Masanori Ooshima, Eiji Hayashi
  • Patent number: 10361315
    Abstract: Fabricating a semiconductor device includes receiving a semiconductor structure including a substrate, a fin formed on a portion of the substrate, and a first hard mask disposed on a top surface of the fin. A bottom spacer is formed on the substrate in contact with a bottom portion of the fin. A top spacer is formed in contact with a top portion of the fin. A lateral recess is formed in the substrate under the bottom spacer. A first epitaxy upon the bottom spacer within the lateral recess and a second epitaxy upon the top spacer are simultaneously grown. The first epitaxy forms a bottom source and drain and the second epitaxy forms a top source and drain.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chun-Chen Yeh, Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Cheng Chi, Chen Zhang
  • Patent number: 10355127
    Abstract: The present technique relates to a semiconductor device including a current sensor, which can improve the electrostatic discharge ruggedness. The semiconductor device includes: a first switching element through which a main current flows; and a second switching element through which a sense current flows. The first switching element includes a first gate oxide film formed in contact with a first base layer sandwiched between a first source layer and a drift layer. The second switching element includes a second gate oxide film formed in contact with a second base layer sandwiched between a second source layer and the drift layer. A part of the second gate oxide film including a portion covering the second base layer is thicker than the first gate oxide film.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: July 16, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Eisuke Suekawa
  • Patent number: 10342138
    Abstract: A chip part includes a substrate having a first main surface on one side thereof and a second main surface on the other side thereof, a functional device famed at a first main surface side of the substrate, an external terminal formed at the first main surface side of the substrate and electrically connected to the functional device, and a light diffusion reflection structure formed at a second main surface side of the substrate and diffusely reflecting light irradiated toward the second main surface of the substrate.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: July 2, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Yasuhiro Kondo, Katsuya Matsuura, Hiroshi Tamagawa
  • Patent number: 10340343
    Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, a pair of source/drain regions and a a threshold voltage adjusting region. The gate electrode is over the semiconductor substrate. The channel region is between the semiconductor substrate and the gate electrode. The source/drain regions are adjacent to two opposing sides of the channel region in a channel length direction. The threshold voltage adjusting region is adjacent to two opposing sides of the channel region in a channel width direction, wherein the threshold voltage adjusting region and the channel region have the same doping type.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: July 2, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
  • Patent number: 10332922
    Abstract: The present disclosure relates to a solid-state imaging device and a manufacturing method of the same, and an electronic apparatus, capable of more reliably suppressing occurrence of color mixing. A trench is formed between PDs so as to be opened to a light receiving surface side of a semiconductor substrate on which a plurality of the PDs, each of which receives light to generate charges, are formed, an insulating film is embedded in the trench and the insulating film is laminated on a back surface side of the semiconductor substrate. Then, a light shielding portion is formed so as to be laminated on the insulating film and to have a convex shape protruding to the semiconductor substrate at a location corresponding to the trench. The present technology can be applied to a back surface irradiation type CMOS solid-state imaging device.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 25, 2019
    Assignee: Sony Corporation
    Inventor: Yuki Miyanami