Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.

Abstract: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a second conductive line disposed adjacent to the first conductive line, surrounded by the dielectric layer and extended parallel to the first conductive line; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via substantially parallel to the first surface of the substrate, wherein the cross section of the conductive via is at least partially protruded from the first conductive line towards the second conductive line. Further, a method of manufacturing the semiconductor structure is also disclosed.

Abstract: IC structures that include transmission line structures to be integrated with III-N devices are disclosed. An example transmission line structure includes a transmission line of an electrically conductive material provided above a stack of a III-N semiconductor material and a polarization material. The transmission line structure further includes means for reducing electromagnetic coupling between the line and charge carriers present below the interface of the polarization material and the III-N semiconductor material. In some embodiments, said means include a shield material of a metal or a doped semiconductor provided over portions of the polarization material that are under the transmission line. In other embodiments, said means include dopant atoms implanted into the portions of the polarization material that are under the transmission line, and into at least an upper portion of the III-N semiconductor material under such portions of the polarization material.

Abstract: In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm2 and lower than or equal to 0.5 W/cm2 is supplied to an electrode provided in the treatment chamber.

Abstract: A display device, includes a substrate having at least two colored subpixels and a white subpixel separately arranged thereon; a first anode having a first thickness at each of the colored subpixels on the substrate; a second anode, having a thickness smaller than the first thickness, at the white subpixel on the substrate; an organic stack comprising a first stack having a first blue emission layer, a second stack having a second blue emission layer, and a third stack having at least one of emission layers having a longer wavelength than the blue emission layers, which are provided in sequence on the first anode in the colored subpixel and the second anode in the white subpixel; a cathode over the organic stack; and a compensation pattern between the second anode and the substrate.

Abstract: One or more embodiments are directed to establishing electrical connections through silicon wafers with low resistance and high density, while at the same time maintaining processability for further fabrication. Such connections through silicon wafers enable low resistance connections from the top side of a silicon wafer to the bottom side of the silicon wafer.

Abstract: A method for manufacturing three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is formed and bonded to a first IC die by a first bonding structure. A third IC die is formed and bonded to the second IC die by a second bonding structure. The second bonding structure is formed between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. In some further embodiments, the second bonding structure is formed by forming conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.

Abstract: An image sensor includes an insulating pattern disposed on a semiconductor substrate and having an opening, a color filter disposed within the opening of the insulating pattern, a capping insulating layer disposed on the color filter, a first electrode disposed on the capping insulating layer and having a portion overlapping with the color filter, a separation structure surrounding a side surface of the first electrode, and a photoelectric layer disposed on the first electrode. The separation structure includes a first insulating layer and a second insulating layer formed of different material.

Abstract: A display device includes signal lines and pixels connected thereto. A first pixel includes a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode, a first source region, and a second drain region facing the first source region, with the first channel region interposed between the first source region and the second drain region. A third transistor includes a third gate electrode, a third channel region overlapping the third gate electrode, a third drain region connected to the first gate electrode, and a third source region facing the third drain region with the third channel region interposed between the third source region and the third drain region. A shielding part overlaps a boundary between the third source region and the third channel region and does not overlap a boundary between the third drain region and the third channel region.

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

Abstract: A pixel definition layer, a display substrate, a display device and an inkjet printing method are provided. The pixel definition layer includes a first pixel definition layer and a second pixel definition layer. The first pixel definition layer includes first openings, which include a first sub-pixel opening and a second sub-pixel opening; and an opening size of the second sub-pixel opening is larger than an opening size of the first sub-pixel opening. The second pixel definition layer is on the first pixel definition layer, and includes second openings, the second openings include a fourth sub-pixel opening and a fifth sub-pixel respectively corresponding to and connecting to the first sub-pixel opening and the second sub-pixel opening. A difference between opening sizes of the fourth sub-pixel opening and the first sub-pixel opening is larger than a difference between opening sizes of the fifth sub-pixel opening and the second sub-pixel opening.

Abstract: A display panel, a display screen, and a display terminal are provided. The display panel includes a substrate and a plurality of wavy first electrodes disposed on the substrate. The plurality of first electrodes extend in parallel in the same direction and have an interval between adjacent first electrodes. In an extending direction of the first electrode, a width of the first electrode changes continuously or intermittently, and the interval changes continuously or intermittently.

Abstract: A display device includes: a substrate including a display area and a peripheral area outside the display area; a plurality of display elements arranged in the display area; and a pad disposed in the peripheral area and having a multi-layered structure, where the multi-layered structure of the pad includes: a metal layer; a conductive protective layer on a top surface of the metal layer; and a metal thin film on a top surface of the conductive protective layer.

Abstract: An organic light emitting diode display panel is provided, including a first substrate, a second substrate opposite to the first substrate, at least one first light emitting layer on a side of the first substrate facing the second substrate, at least one second light emitting layer on the side of the first substrate facing the second substrate, the at least one second light emitting layer being separated from the at least one first light emitting layer, and at least two third light emitting layers on a side of the second substrate facing the first substrate. The at least one first light emitting layer and the at least one second light emitting layer are aligned with corresponding ones of the at least two third light emitting layers.

Abstract: A photoelectric conversion element according to an embodiment of the present disclosure includes: a first electrode; a second electrode opposed to the first electrode; and an organic photoelectric conversion layer provided between the first electrode and the second electrode and formed using a plurality of materials having average particle diameters different from each other, the plurality of materials including at least fullerene or a derivative thereof.

Abstract: The present disclosure discloses a display panel and a display device. The display device includes a first display area and a second display area, where the first display area includes a plurality of first sub-pixel units, and each of the first sub-pixel units includes a first light emitting device and a driving circuit for driving the first light emitting device to emit light; where the second display area includes a plurality of second sub-pixel units and a plurality of first voltage signal lines, each of the second sub-pixel units includes a second light emitting device, and the first voltage signal lines are directly and electrically connected to anodes of the second light emitting devices.

Abstract: The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes: a backplane; a transistor layer on a side of the backplane; a first planarization layer on a side of the transistor layer away from the backplane; an auxiliary cathode layer on a side of the first planarization layer away from the transistor layer; a second planarization layer on a side of the auxiliary cathode layer away from the first planarization layer; and a light-emitting element layer on a side of the second planarization layer away from the auxiliary cathode layer. The light-emitting element layer includes a primary cathode layer electrically connected to the auxiliary cathode layer.

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. A third IC die is bonded to the second IC die by a second bonding structure. The second bonding structure is arranged between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. The second bonding structure further comprises conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.