Patents Examined by Daniel P Shook
  • Patent number: 10510756
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Patent number: 10510661
    Abstract: Semiconductor devices and methods of forming the same are provided. One of the semiconductor devices comprises a conductive layer, a first dielectric layer disposed over the conductive layer, a magnetic layer disposed over the first dielectric layer, and a plurality of tantalum layers and a plurality of tantalum oxide layers alternately disposed between the magnetic layer and the first dielectric layer.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hon-Lin Huang, Chen-Shien Chen, Chin-Yu Ku, Kuan-Chih Huang, Wei-Li Huang
  • Patent number: 10508365
    Abstract: A method for producing a semiconductor layer (3), including the following method steps: A creating a release layer (2) on a carrier substrate (1); B applying a semiconductor layer (3) to the release layer (2); C detaching the semiconductor layer (3) from the carrier substrate. The invention is characterized in that, in method step A, the release layer (2) is created so as to fully cover at least a processing side of the carrier substrate, in that, in method step B, the semiconductor layer (3) is applied so as to fully cover the release layer (2) at least on the processing side and partially overlap one or more peripheral sides (5a, 5b) of the carrier substrate and in that, between method steps B and C, in a method step C0, regions of the semiconductor layer (3) that overlap a peripheral side are removed. The invention also relates to a semiconductor wafer, to a device for edge correction, to a detaching unit and to a device for producing a semiconductor layer.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: December 17, 2019
    Assignee: NexWafe GmbH
    Inventors: Stefan Reber, Kai Schillinger, Frank Siebke
  • Patent number: 10510698
    Abstract: A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 10504796
    Abstract: A semiconductor device includes an n-channel, a p-channel, a first gate dielectric layer, a second gate dielectric layer, a second dielectric sheath layer, and a metal gate. The first gate dielectric layer is around the n-channel. The first dielectric sheath layer is around the first gate dielectric layer. The second gate dielectric layer is around the p-channel. The second dielectric sheath layer is around the second gate dielectric layer, in which the first dielectric sheath layer and the second dielectric sheath layer comprise different materials. The metal gate electrode is around the first dielectric sheath layer and the second dielectric sheath layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Tzu-Chiang Chen, Cheng-Hsien Wu, Chih-Chieh Yeh, Chih-Sheng Chang
  • Patent number: 10505080
    Abstract: A lighting device is specified. The lighting device comprises a phosphor having the general molecular formula (MA)a(MB)b(MC)c(MD)d(TA)e(TB)f(TC)g(TD)h(TE)i(TF)j(XA)k(XB)l(XC)m(XD)n:E. In this case, MA is selected from a group of monovalent metals, MB is selected from a group of divalent metals, MC is selected from a group of trivalent metals, MD is selected from a group of tetravalent metals, TA is selected from a group of monovalent metals, TB is selected from a group of divalent metals, TC is selected from a group of trivalent metals, TD is selected from a group of tetravalent metals, TE is selected from a group of pentavalent elements, TF is selected from a group of hexavalent elements, XA is selected from a group of elements which comprises halogens, XB is selected from a group of elements which comprises O, S and combinations thereof, XC=N and XD=C and E=Eu, Ce, Yb and/or Mn. The following furthermore hold true: a+b+c+d=t; e+f+g+h+i+j=u; k+l+m+n=v; a+2b+3c+4d+e+2f+3g+4h+5i+6j?k?2l?3m?4n=w; 0.8?t?1; ?3.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: December 10, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Markus Seibald, Dominik Baumann, Tim Fiedler, Stefan Lange, Hubert Huppertz, Daniel Dutzler, Thorsten Schroeder, Daniel Bichler, Simon Peschke
  • Patent number: 10497765
    Abstract: An organic light-emitting display panel and a display apparatus are provided. An exemplary organic light-emitting display panel includes a substrate; an array layer disposed on the substrate and a display layer disposed on the array layer. The display layer includes an anode layer, a pixel definition layer having a plurality of the openings exposing the anode layer, an organic light-emitting material layer filled in the openings and connecting with the anode layer, and a cathode layer disposed on the organic light-emitting layer. The plurality of openings of the pixel definition layer includes a plurality of first openings and a plurality of second openings. Along a direction perpendicular to the organic light-emitting display panel, a height of a sidewall of at least a portion of a first opening is greater than a height of a sidewall of a second opening.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 3, 2019
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Haijing Chen, Ming Yang, Yingteng Zhai, Guofeng Zhang
  • Patent number: 10490593
    Abstract: An active matrix image sensing device includes an image sensing substrate and a scintillator substrate. The image sensing substrate has a plurality of image sensing pixels. The scintillator substrate is disposed opposite to the image sensing substrate and includes a first substrate, a plurality of guiding members, a reflective layer and a scintillator layer. The guiding members are disposed on the first substrate and protruded from the first substrate toward the image sensing substrate. The guiding members are located corresponding to the image sensing pixels, respectively. The reflective layer is disposed on the guiding members, and the scintillator layer is disposed between the reflective layer and the image sensing substrate.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 26, 2019
    Assignee: Innolux Corporation
    Inventor: Chih-Hao Wu
  • Patent number: 10483198
    Abstract: Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Min-Tih Ted Lai, Tyler Leuten, Florence R. Pon
  • Patent number: 10483123
    Abstract: A method for forming a well providing access to a sensor pad includes patterning a first photoresist layer over a dielectric structure disposed over the sensor pad; etching a first access into the dielectric structure and over the sensor pad, the first access having a first characteristic diameter; patterning a second photoresist layer over the dielectric structure; and etching a second access over the dielectric structure and over the sensor pad. The second access has a second characteristic diameter. The first and second accesses overlapping. A diameter ratio of the first characteristic diameter to the second characteristic diameter is not greater than 0.7. The first access exposes the sensor pad. The second access has a bottom depth less than a bottom depth of the first access.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: November 19, 2019
    Assignee: LIFE TECHNOLOGIES CORPORATION
    Inventors: Phil Waggoner, Jordan Owens
  • Patent number: 10483217
    Abstract: Representative implementations of devices and techniques provide reinforcement for a carrier or a package. A reinforcement layer is added to a surface of the carrier, often a bottom surface of the carrier that is generally under-utilized except for placement of terminal connections. The reinforcement layer adds structural support to the carrier or package, which can be very thin otherwise. In various embodiments, the addition of the reinforcement layer to the carrier or package reduces warpage of the carrier or package.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: November 19, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Sangil Lee, Craig Mitchell, Gabriel Z. Guevara, Javier A. Delacruz
  • Patent number: 10468527
    Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Wei Yang, Chih-Chang Hung, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • Patent number: 10461143
    Abstract: A transistor substrate may include a base substrate, a data line, a conductive layer, a semiconductor layer, a gate electrode, and a pixel electrode. The data line may directly contact the base substrate. The conductive layer may directly contact the base substrate and may be spaced from the data line. The semiconductor layer may overlap the conductive layer, may be spaced from the conductive layer, and may include a source electrode and a drain electrode. The source electrode may be electrically connected to the data line. The gate electrode may overlap the semiconductor layer. The pixel electrode may be electrically connected to the drain electrode.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 29, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae Hyun Park, Sang Kyung Lee, Jong Moo Huh
  • Patent number: 10446393
    Abstract: A method for forming a silicon-containing epitaxial layer is disclosed. The method may include, heating a substrate to a temperature of less than approximately 950° C. and exposing the substrate to a first silicon source comprising a hydrogenated silicon source, a second silicon source, a dopant source, and a halogen source. The method may also include depositing a silicon-containing epitaxial layer wherein the dopant concentration within the silicon-containing epitaxial layer is greater than 3×1021 atoms per cubic centimeter.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: October 15, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Nupur Bhargava, John Tolle, Joe Margetis, Matthew Goodman, Robert Vyne
  • Patent number: 10438888
    Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Shiro Uchiyama
  • Patent number: 10439059
    Abstract: A transistor includes a first gate-controlled region having a first threshold voltage and a second gate-controlled region in parallel with the first gate-controlled region. The second gate-controlled region has a second threshold voltage different form the first threshold voltage.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 8, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Tomas Apostol Palacios, Sameer Jayanta-Joglekar, Ujwal Radhakrishna
  • Patent number: 10439144
    Abstract: The present invention relates to: an organic compound represented by a combination of Chemical Formulas 1 and 2; an organic optoelectronic device comprising the organic compound; and a display device.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: October 8, 2019
    Assignee: UNIVERSITY-INDUSTRY COOPERATEON GROUP OF KYUNG HEE UNIVERSITY
    Inventors: JongWook Park, JaeHyun Lee
  • Patent number: 10431616
    Abstract: Methods, systems, apparatus, including computer-readable media storing executable instructions, for color filter arrays for image sensors. In some implementations, an imaging device includes a color filter array arranged to filter incident light. The color filter array has a repeating pattern of color filter elements. The color filter elements include yellow filter elements, green filter elements, and blue filter elements. The imaging device includes an image sensor having photosensitive regions corresponding to the color filter elements. The photosensitive regions are configured to respectively generate electrical signals indicative of intensity of the color-filtered light at the photosensitive regions. The imaging device includes one or more processors configured to generate color image data based on the electrical signals from the photosensitive regions.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 1, 2019
    Assignee: Google LLC
    Inventors: Jyrki A. Alakuijala, Zoltan Szabadka
  • Patent number: 10431611
    Abstract: A method for manufacturing a thin film transistor, a method for manufacturing an array substrate, an array substrate, and a display device are provided. The method for manufacturing the thin film transistor includes: forming an active layer on a base substrate; forming a metal layer on the surface of the active layer; and processing the metal layer using a patterning process for one time and an oxidation treatment process, so that the metal layer forms a source electrode, a drain electrode and a passivation layer; wherein the source electrode and the drain electrode are in contact with the active layer, and the passivation layer is formed on a side of the source electrode and the drain electrode away from the active layer.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: October 1, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xianxue Duan, Kui Gong
  • Patent number: 10431689
    Abstract: The disclosure discloses a thin film transistor and a display panel. The thin film transistor includes a gate, a source, a drain, an active layer, and a heat transmitting layer; wherein the heat transmitting layer is arranged on a side of the active layer. In the disclosure, the heat of the active layer may be promptly conducted to the surrounding environment, so as to prevent the self-heating effect of the thin film transistor from affecting the normal working state.
    Type: Grant
    Filed: November 23, 2017
    Date of Patent: October 1, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xiao Wang