Abstract: The invention relates to a method of providing a structure by depositing a layer on a substrate in a reactor. The method comprising: introducing a silicon halide precursor in the reactor; introducing a reactant gas comprising oxygen in the reactor; and, providing an energy source to create a plasma from the reactant gas so that the oxygen reacts with the first precursor in a layer comprising silicon dioxide.

Abstract: The disclosure provides a flexible display panel, a method for fabricating the same, and a flexible display device. A flexible display panel according to an embodiment of the disclosure includes a flexible substrate comprising a display area and a non-display area, the non-display area is provided with a bendable area; a display element arranged in the display area of the flexible substrate; a flexible element arranged in the bendable area of the flexible substrate; a backside protection film arranged on a side of the flexible substrate away from the display element; the backside protection film is provided with a groove; a length direction of the groove is parallel to a direction of a bending axis of the bendable area.

Abstract: An organic light emitting display (OLED) screen and a terminal related to the field of terminal technologies, where the OLED screen includes an encapsulation layer and a substrate disposed below the encapsulation layer, in a first part of the OLED screen, the encapsulation layer is bonded to the substrate, and in a second part of the OLED screen, the OLED screen further includes a light emitting layer, where the light emitting layer is disposed between the encapsulation layer and the substrate, and the light emitting layer includes red light emitting pixels, green light emitting pixels, and blue light emitting pixels.

Abstract: An LED display module is disclosed. The LED display module includes: a micro-LED array including a plurality of pixel units arrayed in a matrix with rows and columns, each of the pixel units including a red LED, a green LED, and a blue LED; a substrate including a top layer on which the pixel units are mounted, a first layer located under the top layer, and a second layer located under the first layer; and pairs of electrode pads disposed on the substrate and to which first electrodes and second electrodes of the LEDs of the pixel units are connected. The distances between peripheral portions of the paired electrode pads are longer than the distances between central portions thereof.

Abstract: A display panel includes a base substrate including a first surface; another base substrate including a second surface disposed face the first surface; a first insulating layer disposed above the first surface of the base substrate, a plurality of grooves being disposed in a surface of the first insulating layer away from the base substrate; a first conductive layer disposed at a side of the first insulating layer away from the base substrate, the first conductive layer at least covering bottom faces and side walls of the plurality of grooves; a plurality of support portions disposed above the second surface of the another base substrate; and a second conductive layer disposed at a side of the plurality of support portions away from the another base substrate, the second conductive layer at least covering surfaces of the plurality of support portions facing away from the another base substrate and side faces of the plurality of support portions.

Abstract: Integrated circuit structures including device terminal interconnect pillar structures, and fabrication techniques to form such structures. Following embodiments herein, a small transistor terminal interconnect footprint may be achieved by patterning recesses in a gate interconnect material and/or a source or drain interconnect material. A dielectric deposited over the gate interconnect material and/or source or drain interconnect material may be planarized to expose portions of the gate interconnect material and/or drain interconnect material that were protected from the recess patterning. An upper level interconnect structure, such as a conductive line or via, may contact the exposed portion of the gate and/or source or drain interconnect material.

Abstract: A display panel, a display screen, and a terminal device are provided. The display panel includes: a substrate; and a plurality of first electrodes disposed on the substrate, the plurality of the first electrodes extending in parallel with each other in a extending direction, and two adjacent first electrodes having an interval therebetween, a width of the first electrode changes continuously or intermittently in the extending direction of the first electrodes, two edges of the first electrode in the extending direction thereof are wavy lines, crests and troughs of the wavy line are both curves, and a radius of curvature of the curve at the crest is different from a radius of curvature of the curve at the trough.

Abstract: A backend electrostatic discharge (ESD) diode device structure is presented comprising: a first structure comprising a first material, wherein the first material includes metal; a second structure adjacent to the first structure, wherein the second structure comprises a second material, wherein the second material includes a semiconductor or an oxide; and a third structure adjacent to the second structure, wherein the third structure comprises of the first material, wherein the second structure is between the first and third structures. Other embodiments are also disclosed and claimed.

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

Abstract: A semiconductor device includes a semiconductor body having opposing first and second surfaces in a vertical direction, a first semiconductor region of a first doping type electrically coupled to a first terminal, a second semiconductor region of a second doping type electrically coupled to a second terminal, and a third semiconductor region of the second doping type, but less highly doped than the second semiconductor region, extending in an active region of the semiconductor device from the first to the second semiconductor region in the vertical direction. A horizontal field-stop-region of the first doping type extends in an edge region of the device from the first semiconductor region into the semiconductor body in the vertical direction, such that it directly adjoins the first and second semiconductor regions. A horizontal compensation region of the first doping type extends from the horizontal field-stop-region into the second semiconductor region in a horizontal direction.

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

Abstract: An electroluminescent display and illuminating device and a manufacturing method thereof are provided. Layers of light-emitting devices of an electroluminescent display and an electroluminescent illuminator are assembled, and the two devices share an electrode in a middle of a laminated structure, thereby realizing a display function on one side of the device and realizing a illumination function on the other side of the device, so that a shape design of a product can be more flexible.

Abstract: An imaging element according to an embodiment of the present disclosure includes: a first electrode and a second electrode facing each other; and a photoelectric conversion layer including a p-type semiconductor and an n-type semiconductor, and provided between the first electrode and the second electrode, in which the photoelectric conversion layer has an exciton charge separation rate of 1×1010 s?1 to 1×1016 s?1 both inclusive in a p-n junction surface formed by the p-type semiconductor and the n-type semiconductor.

Abstract: The present invention provides a method for depositing an organic-inorganic perovskite, the method comprising the step of depositing a perovskite precursor solution comprising one or more organic cation, wherein said precursor solution preferably deposited by inkjet printing. The method is particularly useful in the manufacture of perovskite solar cells. For depositing the perovskite, a perovskite precursor solution or ink is preferably used, which comprises an organic cation carrying an anchoring group, such as 5-ammonium valeric acid. Surprisingly, the presence of the latter compound renders the precursor solutions stable and suitable for inkjet printing.

Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.

Abstract: A display device includes a first substrate, a display region arranged with a pixel including a light emitting element above the first substrate, a first inorganic insulating layer covering the display region, an organic insulating layer arranged above the first inorganic insulating layer, a second inorganic insulating layer arranged above the organic insulating layer and having a N—H bond total weight measured by an FT-IR method lower than a N—H bond total weight per unit [% area] of the first inorganic insulating layer, and a polarizing plate arranged above the second inorganic insulating layer.

Abstract: An organic lighting apparatus can include a substrate; and a plurality of light-emitting portions disposed in a central area of the substrate, each of the plurality of light-emitting portions has a structure including: a first electrode, an organic light-emitting layer, a second electrode, a non-light-emitting area, a light-emitting area, and an electric current injection line disposed in the non-light emitting area, in which the electric current injection lines of at least two light-emitting portions have different lengths.

Abstract: Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.

Abstract: A device comprising a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, and a first gate surrounding the first plurality of channels. The first plurality of channels is located between the first source and the first drain. At least one channel includes silicon germanium (SiGe). The transistor is a field effect transistor (FET). The transistor is a gate all around (GAA) FET. The transistor may be configured to operate as a negative channel metal oxide semiconductor (NMOS) transistor. The transistor may be configured to operate as a positive channel metal oxide semiconductor (PMOS) transistor.

Abstract: A method of forming a gate isolation plug for FinFETs includes forming an elongated gate, forming first and second spacers in contact with first and second sidewalls of the elongated gate, separating the elongated gate into first and second gate portions using first and second etching steps, and forming a gate isolation plug between the first and second gate portions, wherein a length of the gate isolation plug is greater than a length of either of the first or second gate portions.