Patents Examined by Daniel Shook
  • Patent number: 10164058
    Abstract: A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: December 25, 2018
    Assignees: FUJI ELECTRIC CO., LTD., Japan Aerospace Exploration Agency
    Inventors: Shuhei Tatemichi, Shunji Takenoiri, Masanori Inoue, Yuji Kumagai, Satoshi Kuboyama, Eiichi Mizuta
  • Patent number: 10163751
    Abstract: A package structure includes a first package layer, a second package layer, and a chip layer positioned between the first package layer and the second package layer. The first package layer includes an electrical signal structure electrically isolated from a first thermal conduction structure. The chip layer includes an integrated circuit (IC) chip electrically connected to the electrical signal structure, a molding material, and a through-via positioned in the molding material. The first thermal conduction structure, the through-via, and the second thermal conduction structure are configured as a low thermal resistance path from the IC chip to a surface of the second package layer opposite the chip layer.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ying-Chih Hsu, Alan Roth, Chuei-Tang Wang, Chih-Yuan Chang, Eric Soenen, Chih-Lin Chen
  • Patent number: 10157853
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface, which includes an element forming region and an element isolation region, and a second surface opposite to the first surface, a semiconductor element formed on the semiconductor substrate in the element forming region, an insulator formed on the semiconductor substrate in the element isolation region, a first wiring layer formed on the first surface of the semiconductor substrate, the first wiring layer being connected to the semiconductor element, an alignment mark formed on the semiconductor substrate in the element isolation region, the entire alignment mark overlapping with the insulator in a plan view of the semiconductor device, and a second wiring layer formed on the second surface of the semiconductor substrate.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: December 18, 2018
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Azusa Ozawa
  • Patent number: 10153293
    Abstract: A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows. The surface of an element isolation region STI1 surrounding the p-type well PW1 is set lower than the surface of an element isolation region STI2 surrounding the p-type well PW2 or the n-type well (H1<H2). By making the surface of the element isolation region STI1 receded and lowered, the effective channel width of both a control transistor and a memory transistor can be increased. Since the surface of the element isolation region STI2 is not made receded, an undesired film can be prevented from being residual over a dummy gate electrode.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: December 11, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tamotsu Ogata
  • Patent number: 10153314
    Abstract: The present technology relates to a semiconductor apparatus, a solid-state image pickup device, an image pickup apparatus, and an electronic apparatus capable of improving impedance characteristics while preventing an occurrence of a flare and an interference due to a bonding jig, and achieving downsizing an apparatus. By aligning the heights of a cover glass and a semiconductor device, a distance between the cover glass and the semiconductor device is set to be minimum, and thus it is possible to suppress an occurrence of a flare due to incident light reflected on a side surface of the semiconductor device, and improve the impedance characteristics of the semiconductor device and the semiconductor image pickup device. Further, the interference of the jig used for the semiconductor device is reduced. The present technology can be applied to a CMOS image sensor.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: December 11, 2018
    Assignee: SONY CORPORATION
    Inventor: Satoru Wakiyama
  • Patent number: 10153376
    Abstract: A semiconductor device including an oxide semiconductor and an organic resin film is manufactured in the following manner. Heat treatment is performed on a first substrate provided with an organic resin film over a transistor including an oxide semiconductor in a reduced pressure atmosphere; handling of the first substrate is performed in an atmosphere containing moisture as little as possible in an inert gas (e.g., nitrogen) atmosphere with a dew point of lower than or equal to ?60° C., preferably with a dew point of lower than or equal to ?75° C. without exposing the first substrate after the heat treatment to the air; and then, the first substrate is bonded to a second substrate that serves as an opposite substrate.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: December 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiharu Hirakata, Nozomu Sugisawa, Ryo Hatsumi, Tetsuji Ishitani
  • Patent number: 10141307
    Abstract: A semiconductor device includes an isolation layer, first and second fin structures, a gate structure and a source/drain structure. The isolation layer is disposed over a substrate. The first and second fin structures are disposed over the substrate, and extend in a first direction in plan view. Upper portions of the first and second fin structures are exposed from the isolation layer. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The source/drain structure is formed on the upper portions of the first and second fin structures, which are not covered by the first gate structure and exposed from the isolation layer, and wraps side surfaces and a top surface of each of the exposed first and second fin structures. A void is formed between the source/drain structure and the isolation layer.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Ka-Hing Fung
  • Patent number: 10131533
    Abstract: A MEMS device includes a first structure including at least one first bump over a surface of the first structure, a second structure including a first side facing the surface of the first bump and a second side opposite to the first side, and a gap between the first structure and the second structure. The first structure and the second structure are configured to move in relation to each other. The first bump includes a plurality of first teeth over a stop surface of the first bump.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shang-Ying Tsai, Kuei-Sung Chang, Yueh Kang Lee
  • Patent number: 10134735
    Abstract: A heterogeneously integrated semiconductor devices includes a base substrate; a Ge-containing film formed on the base substrate; a PMOSFET transistor having a first fin formed on the Ge-containing film; and a NMOSFET transistor having a second fin formed on the Ge-containing film; wherein the PMOSFET transistor and the NMOSFET transistor compose a CMOS transistor, and the first fin comprises Ge-containing material and the second fin comprises a Group III-V compound.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: November 20, 2018
    Assignees: National Applied Research Laboratories, EPISTAR Corporation
    Inventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
  • Patent number: 10135019
    Abstract: A lighting apparatus using an organic light-emitting diode and a method of fabricating the same according to the present disclosure are characterized in that contact electrodes are formed by laser ablation and printing after an organic emissive material, a conductive film as a cathode, and passivation layers are deposited on the entire surface of a substrate. The lighting apparatus may be fabricated in a simplified manner without using an open mask (metal mask), which is a complicated tool, and may be useful especially in roll-to-roll manufacturing.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: November 20, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Shinbok Lee, Taejoon Song, Namkook Kim, Soonsung Yoo, Hwankeon Lee
  • Patent number: 10128167
    Abstract: A semiconductor module is provided, including: a cooling-target device; a first cooling unit on which the cooling-target device is placed and that has a flow channel through which a refrigerant for cooling the cooling-target device flows; and a second cooling unit to which the first cooling unit is fixed and that has a flow channel coupled with the flow channel of the first cooling unit. Also, a semiconductor module manufacturing method is provided, including: placing a cooling-target device on a first cooling unit that has a flow channel through which a refrigerant for cooling the cooling-target device flows; and fixing the first cooling unit to a second cooling unit that has a flow channel coupled with the flow channel of the first cooling unit.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: November 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akira Morozumi, Hiromichi Gohara, Yoshitaka Nishimura
  • Patent number: 10115691
    Abstract: A module, comprising an electronic component having a first electrode, a mounting board having a second electrode, a solder-bump configured to connect the first electrode and the second electrode, and a thermoplastic resin member configured to contact both the first electrode and the second electrode and cover the solder-bump, so as to form a space between the electronic component and the mounting board.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: October 30, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Ichiro Kataoka, Takahiro Hachisu, Tadashi Kosaka
  • Patent number: 10109667
    Abstract: An imaging device that has a structure where a transistor is used in common by a plurality of pixels and is capable of imaging with a global shutter system is provided. A transistor that resets the potential of a charge detection portion, a transistor that outputs a signal corresponding to the potential of the charge detection portion, and a transistor that selects a pixel are used in common by the plurality of pixels. A transistor is provided between a power supply line and a photoelectric conversion element. Exposure is performed by turning on the transistor. Imaging data is retained in a charge retention portion by turning off the transistor.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 23, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Naoto Kusumoto
  • Patent number: 10103234
    Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: October 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara
  • Patent number: 10103347
    Abstract: A transparent electrode includes: a substrate; and a conductive metal layer on the substrate. The conductive metal layer has a thin metal wire and a plating layer. The plating layer covers the thin metal wire. The transparent electrode further includes a transparent conductive layer on a surface of the substrate on a side on which the thin metal wire is formed. The transparent conductive layer covers the substrate and the conductive metal layer. The thin metal wire is formed using a metal nanoparticle ink or a metal complex ink.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: October 16, 2018
    Assignee: KONICA MINOLTA, INC.
    Inventors: Shigeru Kojima, Kazuhiro Yoshida, Shun Furukawa, Takeshi Hakii
  • Patent number: 10096784
    Abstract: Disclosed are a compound for an organic optoelectric device represented by Chemical Formula 1, a composition for an organic optoelectric device, an organic optoelectric device including the same, and a display device. Details of Chemical Formula 1 are the same as those defined in the specification.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: October 9, 2018
    Assignees: Samsung SDI Co., Ltd., Samsung Electronics Co., Ltd.
    Inventors: Byungku Kim, Dong Min Kang, Jinhyun Lui, Bum Woo Park, Eun Sun Yu, Yuna Jang, Sung-Hyun Jung, Pyeongseok Cho
  • Patent number: 10096719
    Abstract: In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm2 and lower than or equal to 0.5 W/cm2 is supplied to an electrode provided in the treatment chamber.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: October 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenichi Okazaki, Toshinari Sasaki, Shuhei Yokoyama, Takashi Hamochi
  • Patent number: 10090339
    Abstract: Disclosed is a radio frequency (RF) switch that includes a substrate and a plurality of elongated drain/source (D/S) diffusion regions laterally disposed in parallel with one another and separated by a plurality of elongated channel regions. A plurality of elongated D/S resistor regions extends between an adjacent pair of plurality of elongated D/S diffusion regions, and a plurality of elongated gate structures resides over corresponding ones of the elongated channel regions. A silicide layer resides over a majority of at least top surfaces of the plurality of the elongated D/S diffusion regions and the plurality of elongated gate structures, wherein less than a majority of each of the plurality of the elongated D/S resistor regions are covered by the silicide layer.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: October 2, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, George Maxim, Baker Scott, Julio C. Costa
  • Patent number: 10090474
    Abstract: A condensed-cyclic compound and an organic light-emitting device including the same, the compound being represented by Formula 1
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: October 2, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Youngkook Kim, Soobyung Ko, Jongwoo Kim, Sanghyun Han, Seokhwan Hwang
  • Patent number: 10084120
    Abstract: A method of producing a light transmissive element includes providing a holding member including an upper surface and a plurality of holes, each of the plurality of holes having at least one inner lateral surface that is a substantially smooth surface and an opening in the upper surface of the holding member; filling the plurality of holes with a wavelength conversion member containing fluorescent particles and a light transmissive member such that the wavelength conversion member is in contact with the inner lateral surface of each of the plurality of holes; molding the wavelength conversion member; and taking out the wavelength conversion member from the holding member after the molding of the wavelength conversion member.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: September 25, 2018
    Assignee: NICHIA CORPORATION
    Inventor: Toru Hashimoto