Abstract: Methods of forming microelectronic package structures are described. Those methods/structures may include forming a high density region on a board comprising a first plurality of conductive structures disposed on a dielectric material on the board, wherein the first plurality of conductive structures comprises a first pitch between individual ones of the first plurality of conductive structures. A low density region on the board comprises a second plurality of conductive structures disposed on the dielectric material, wherein the second plurality of conductive structures comprises a second pitch between individual ones of the second plurality of conductive structures, wherein the second pitch is more than about twice the magnitude of the first pitch.

Abstract: A method of fabricating a fin field-effect transistor (FinFET) device is provided. The method includes forming a carbon-based layer on a plurality of gate structures formed on a semiconductor substrate. Each gate structure overlies at least one fin formed on the semiconductor substrate. The carbon-based layer covers sidewalls of the gate structures. A metal silicide layer overlies the carbon-based layer. The metal silicide layer and carbon-based layer are removed, and a metal layer is formed between adjacent gate structures.

Abstract: A manufacturing method of an epitaxial silicon wafer including a silicon wafer doped with boron and having a resistivity of 100 m?·cm or less and an epitaxial film formed on the silicon wafer includes: growing the epitaxial film on the silicon wafer; and applying a heat treatment on the epitaxial silicon wafer at a temperature of less than 900 degrees C.

Abstract: The present disclosure relates to a solid-state imaging device and a manufacturing method of the same, and an electronic apparatus, capable of more reliably suppressing occurrence of color mixing. A trench is formed between PDs so as to be opened to a light receiving surface side of a semiconductor substrate on which a plurality of the PDs, each of which receives light to generate charges, are formed, an insulating film is embedded in the trench and the insulating film is laminated on a back surface side of the semiconductor substrate. Then, a light shielding portion is formed so as to be laminated on the insulating film and to have a convex shape protruding to the semiconductor substrate at a location corresponding to the trench. The present technology can be applied to a back surface irradiation type CMOS solid-state imaging device.

Abstract: An LED chip package includes a substrate having a metal terminal (gold finger structure). A LED chip set is composed of a plurality of LED chips formed in one piece, and has a plurality of light-emitting areas which are separated from each other. The LED chip set is disposed on the substrate and electrically connected to the metal terminal.

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

Abstract: A light emitting element mounting substrate, including a substrate made from a ceramic; a metal layer provided on the substrate that includes gold or silver as a primary component; and a resin layer provided covering at least a portion of the metal layer. The resin layer includes platinum, and at least one type of oxide of magnesium, calcium, and copper is present on a surface of the metal layer.

Abstract: Magnetoresistive random access memory (MRAM) devices include a first magnetic layer. A tunnel barrier layer is formed on the first magnetic layer. The tunnel barrier includes first regions having a first thickness and second regions having a second thickness that is greater than the first thickness. A second magnetic layer is formed on the tunnel barrier layer.

Abstract: A semiconductor device including an oxide semiconductor and an organic resin film is manufactured in the following manner. Heat treatment is performed on a first substrate provided with an organic resin film over a transistor including an oxide semiconductor in a reduced pressure atmosphere; handling of the first substrate is performed in an atmosphere containing moisture as little as possible in an inert gas (e.g., nitrogen) atmosphere with a dew point of lower than or equal to ?60° C., preferably with a dew point of lower than or equal to ?75° C. without exposing the first substrate after the heat treatment to the air; and then, the first substrate is bonded to a second substrate that serves as an opposite substrate.

Abstract: A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure.

Abstract: A method of manufacturing a semiconductor device includes: forming a lattice defect layer in a substrate having a front surface region where a bipolar element of a pn junction type is formed and a rear surface region opposing the front surface region, the lattice defect layer being formed by injecting a charged particle to a first region in the rear surface region of the substrate; forming a laminated region, in which a first conductivity type impurity region and a second conductivity type impurity region are sequentially laminated from a rear surface side of the substrate toward the first region, in a second region in the rear surface region of the substrate, the first region being positioned deeper than the second region from a rear surface of the substrate; and selectively activating the laminated region by laser annealing after the formation of the laminated region and the lattice defect layer.

Abstract: A method for synthesizing a quantum dot light emitting diode by providing a glass substrate. A QD-LED stack is formed upon the glass substrate. This QD-LED stack is diffused with an active reagent. The QD-LED stack is encapsulated with a curable resin. The curable resin is cured with UV light.

Abstract: A wafer processing method including the steps of storing information on the intervals and positions of metal patterns formed on part of division lines on a wafer into a storage unit of a cutting apparatus, detecting the division lines, forming a cut groove along each division line by using a cutting blade, imaging an area including the cut groove at any position where the metal patterns are not formed, by using an imaging unit included in the cutting apparatus, according to the information on the intervals and positions of the metal patterns previously stored, during the step of forming the cut grooves, and measuring the positional relation between the position of the cut groove and a preset cutting position. Accordingly, kerf check can be performed without being influenced by burrs produced from the metal patterns in cutting the wafer, so that the wafer can be cut with high accuracy.

Abstract: A transistor substrate includes a plurality of first transistors formed between a power supply wire and a first conductive wire, and a plurality of second transistors formed between the power supply wire and a second conductive wire. A length of a portion of the power supply wire between the plurality of second transistors and a drive signal generation circuit is longer than a length of a portion of the power supply wire between the plurality of first transistors and the drive signal generation circuit, and a total sum of channel widths of second channels included in the plurality of second transistors is wider than a total sum of channel widths of first channels included in the plurality of first transistors.

Abstract: An organic electroluminescence display includes a plurality of scan lines, a plurality of data lines, at least one first pixel circuit, and at least one second pixel circuit. The scan lines and the data lines cross. Each of the first and second pixel circuits is electrically connected to one of the scan lines and one of the data lines. The first pixel circuit includes at least one first driving transistor having a first channel in a first channel direction. The second pixel circuit includes at least one second driving transistor having a second channel in a second channel direction. The second channel direction is different from that of the first channel direction.

Abstract: An anodic oxide film structure cutting method is provided. The method includes: an etching step of forming an etched groove by etching one surface of an anodic oxide film having a plurality of anodizing pores along a predetermined cutting line and forming increased-diameter pores by enlarging entrances of the anodizing pores positioned on an inner bottom surface of the etched groove; and a cutting step of cutting the anodic oxide film along the etched groove. Also provided is a unit anodic oxide film structure produced by the cutting method.

Abstract: Embodiments of the invention include a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A metal n-contact is connected to the n-type region. A metal p-contact is in direct contact with the p-type region. An interconnect is electrically connected to one of the n-contact and the p-contact. The interconnect is disposed adjacent to the semiconductor structure.

Abstract: A power semiconductor substrate comprising an insulating planar base, at least one conductor track and at least one contact area as part of the conductor track, wherein a layer of a metallic material is disposed on the contact area by means of pressure sintering. The associated method comprises the steps of: producing a power semiconductor substrate that includes a planar insulating base, conductor tracks and contact areas; arranging a pasty layer, composed of a metallic material and a solvent, on at least one contact area of the power semiconductor substrate; and applying pressure to the pasty layer.

Abstract: A semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type that is between the first electrode and the second electrode. A second semiconductor region is adjacent to the first semiconductor region along a first direction and includes a second conductivity type material. A first insulating region is provided within the second semiconductor region. A third electrode is provided on the first semiconductor region via a second insulating region.

Abstract: Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.