Abstract: Magnetoresistive random access memory devices include a first magnetic layer, a tunnel barrier layer formed on the first magnetic layer, and a second magnetic layer formed on the tunnel barrier layer. The tunnel barrier includes first regions having a first thickness and second regions having a second thickness that is greater than the first thickness. The tunnel barrier layer includes a first barrier layer formed from a first material and a second barrier layer formed from a second material different from the first material, the second layer being present only in the second regions.

Abstract: A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first semiconductor layer, the active region including a drift layer; and a termination region disposed to surround the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region, wherein the upper edge region includes a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type.

Abstract: An imaging device includes a unit pixel cell including: a semiconductor substrate including a first region exposed to a surface of the semiconductor substrate in a first area, and a second region directly adjacent to the first region and exposed to the surface in a second area; a photoelectric converter; a contact plug connected to the second region; a first transistor including the second region as one of a source and a drain, a first electrode covering a first portion of the first area, and a first insulation layer between the first electrode and the semiconductor substrate; a second electrode covering a second portion of the first area; and a second insulation layer between the second electrode and the semiconductor substrate. When seen in a direction perpendicular to the surface, a contact between the second region and the contact plug is located between the first electrode and the second electrode.

Abstract: A high-voltage bipolar semiconductor controlled rectifier (SCR) includes an emitter region having a first polarity and overlying a base region having a second polarity different from the first polarity; a collector region having the first polarity and lying under the base region; an anode region having the second polarity; a first sinker region having the first polarity and contacting the collector region, wherein the anode region is between the first sinker region and the base region; and a second sinker region having the first polarity and contacting the collector region, the second sinker region lying between the anode region and the base region, wherein an extension of the anode region extends under a portion of the second sinker region.

Abstract: A photodetector structure comprises a semiconductor substrate extending substantially along a horizontal plane and having a bulk refractive index and a front surface defining a front side of the photodetector structure. The front surface comprises high aspect ratio nanostructures forming an optical conversion layer having an effective refractive index gradually changing towards the bulk refractive index to reduce reflection of light incident on the photodetector structure from the front side thereof. Further, the semiconductor substrate comprises an induced junction.

Abstract: A semiconductor device includes a substrate structure, multiple fins protruding from the substrate structure, each of the fins having a first portion, a second portion on opposite sides of the first portion, and a third portion at an outer side of the first portion and adjacent to the second portion, a gate structure on the upper surface of the first portion, sidewall spacers on opposite sides of the gate structure and covering the upper surface of the second portion, and source and drain regions outside of the sidewall spacers. The source and drain regions each have an upper surface higher than the second portion upper surface. The first portion protrudes from the second portion. The upper surface of the second portion is lower than the first portion upper surface. The upper surface of the third portion is lower than the second portion upper surface.

Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.

Abstract: Implementations of the present disclosure generally relate to methods and apparatuses for epitaxial deposition on substrate surfaces. More particularly, implementations of the present disclosure generally relate to methods and apparatuses for surface preparation prior to epitaxial deposition. In one implementation, a method of processing a substrate is provided. The method comprises etching a surface of a silicon-containing substrate by use of a plasma etch process, where at least one etching process gas comprising chlorine gas and an inert gas is used during the plasma etch process and forming an epitaxial layer on the surface of the silicon-containing substrate.

Abstract: Disclosed herein is a wafer processing method including a processed position measuring step of imaging an area including a beam plasma generated by applying a pulsed laser beam to a wafer, by using an imaging unit during the formation of a laser processed groove on the wafer, and next measuring the positional relation between the position of the beam plasma and a preset processing position. Accordingly, it is possible to check whether or not the laser processed groove is formed at a desired position, in real time during laser processing. If the position of the laser processed groove is deviated, the processed position can be immediately corrected.

Abstract: A method of fabricating a fin field-effect transistor (FinFET) device is provided. The method includes forming a carbon-based layer on a plurality of gate structures formed on a semiconductor substrate. Each gate structure overlies at least one fin formed on the semiconductor substrate. The carbon-based layer covers sidewalls of the gate structures. A metal silicide layer overlies the carbon-based layer. The metal silicide layer and carbon-based layer are removed, and a metal layer is formed between adjacent gate structures.

Abstract: In one aspect, a Hall Effect sensing element includes a Hall plate having a thickness less than about 100 nanometers an adhesion layer directly in contact with the Hall plate and having a thickness in a range about 0.1 nanometers to 5 nanometers. In another aspect, a sensor includes a Hall Effect sensing element. The Hall Effect sensing element includes a substrate that includes one of a semiconductor material or an insulator material, an insulation layer in direct contact with the substrate, an adhesion layer having a thickness in a range of about 0.1 nanometers to 5 nanometers and in direct contact with the insulation layer and a Hall plate in direct contact with the adhesion layer and having a thickness less than about 100 nanometers.

Abstract: Some embodiments include a method of forming a pattern. A semiconductor substrate has first and second rows extending along a first direction, and which alternate with one another along a second direction. Each of the rows includes course regions that are to be included along patterned structures. The course regions within the first rows are staggered relative to the course regions within the second rows. The patterned structures comprise first segments which extend along a third direction, and comprise second segments which extend along a fourth direction different from the third direction. Patterned masking material is formed across the substrate to define a first pattern having the first segments of the patterned structures, and to define a second pattern having the second segments of the patterned structures. The patterned structures are formed within the first and second patterns defined by the patterned masking material. Some embodiments include apparatuses having finFETs.

Abstract: A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.

Abstract: Methods of forming conductive interconnect structures are described. Those methods/structures may include providing a package substrate comprising a substrate core, and forming at least one conductive interconnect structure disposed on the substrate core. The conductive interconnect structure may comprise a first side that is directly disposed on a surface of the substrate core, and a second side opposite the first side, wherein the second side comprises a greater length than a length of the first side.

Abstract: An image sensor includes a plurality of photoelectric detectors, a plurality of color filters, and at least one pixel isolation region between adjacent ones of the photoelectric detectors. The color filters include a white color filter, and the color filters correspond to respective ones of the photoelectric detectors. The at least one pixel isolation region serves to physically and at least partially optically separate the photoelectric detectors from one another.

Abstract: A semiconductor device includes: a first substrate on which a first field effect transistor is provided; and a second substrate on which a second field effect transistor of a second conductive type is provided; the first and second substrates being bonded to each other at the substrate faces thereof on which the first and second field transistors are provided, respectively; the first field effect transistor and the second field effect transistor being electrically connected to each other.

Abstract: In one embodiment, a bi-directional punch-through semiconductor device can include: a first transistor in a first region of a semiconductor substrate of a first conductivity type, where the first transistor includes a semiconductor buried layer of a second conductivity type in the semiconductor substrate, and a first epitaxy region of an epitaxy semiconductor layer above the semiconductor buried layer, the semiconductor buried layer being configured as a base of the first transistor; and a second transistor coupled in parallel with the first transistor, where the second transistor is in a second region of the semiconductor substrate of the first conductivity type, where the second transistor comprises a second epitaxy region of the epitaxy semiconductor layer above the semiconductor substrate, and a first doped region of the second conductivity type in the second epitaxy region, the first doped region being configured as a base of the second transistor.

Abstract: Provided is a split-gate embedded flash memory cell and method for forming the same. The flash memory cell includes split-gate transistors in which the control gate is aligned with respect to the floating gate without the use of a photolithographic patterning operation to pattern the material from which the control gates are formed. An anisotropic blanket etching operation is used to form the floating gates of the split-gate floating gate transistors alongside sidewalls of a sacrificial layer. Local oxidation of silicon (LOCOS) methods are not needed to form the inter-gate dielectric and therefore high integrity is maintained for the floating transistor gates. The floating transistor gates are formed of charge storage material such as silicon nitride, Si3N4 in some embodiments.

Abstract: In accordance with an example embodiment of this disclosure, a micro-electro-mechanical system (MEMS) device comprises a substrate, a CMOS die, and a MEMS die, each of which comprises a top side and a bottom side. The bottom side of the CMOS die is coupled to the top side of the substrate, and the MEMS die is coupled to the top side of the CMOS die, and there is a cavity positioned between the CMOS die and the substrate. The cavity may be sealed by a sealing substance, and may be filled with a filler substance (e.g., an adhesive) that is different than the sealing substance (e.g., a gaseous or non-gaseous substance). The cavity may be fully or partially surrounded by one or more downward-protruding portions of the CMOS die and/or one or more upward-protruding portions of the substrate.

Abstract: Methods for forming a NW with multiple devices having alternate channel materials and resulting devices are disclosed. Embodiments include forming a first stack of semiconductor layers including a first doped Si layer, a first channel layer, and a second doped Si layer, respectively, on a Si substrate; forming a second stack including a first doped SiGe layer, a second channel layer, and a second doped SiGe layer, respectively, on the first stack; forming a vertical nanowire structure by directional etching, along a three-dimensional plane, the second and first stacks, respectively, down to an upper surface of the Si substrate; forming lower S/D regions and a lower gate-stack surrounding the first stack; forming upper S/D regions and an upper gate-stack surrounding the second stack; and forming contacts to the lower S/D regions, a first gate electrode, an upper S/D region, an upper gate electrode, and the second doped SiGe layer.