Patents Examined by Daniel Tsui
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Patent number: 10095303Abstract: A non-volatile memory system includes a memory controller, where the memory controller includes a first region including a first memory that stores compressed code, and a second region including a second memory that stores decompressed code. Power supplied to the first region and the second region is controlled according to an operation mode of the non-volatile memory system.Type: GrantFiled: April 13, 2015Date of Patent: October 9, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-Won Ahn, Hwa-Seok Oh
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Patent number: 10082984Abstract: A method of operating a storage device that controls input/output of multi-stream data according to a stream ID may include receiving, from a host, a stream control command controlling at least a first stream ID and a second stream ID, determining, in response to the received stream control command, a third stream ID including control commands for the first and second stream IDs, and transmitting the third stream ID to the host.Type: GrantFiled: April 21, 2016Date of Patent: September 25, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Donghun Lee, Isaac Baek, Hyesung Kim
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Patent number: 10055348Abstract: A higher level shared cache of a hierarchical cache of a multi-processor system utilizes transaction identifiers to manage memory conflicts in corresponding transactions. The higher level cache is shared with two or more processors. Transaction indicators are set in the higher level cache corresponding to the cache lines being accessed. The transaction aborts if a memory conflict with the transaction's cache lines from another transaction is detected.Type: GrantFiled: September 2, 2015Date of Patent: August 21, 2018Assignee: International Business Machines CorporationInventors: Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum
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Patent number: 10048883Abstract: In an embodiment, a method can include storing a plurality of volumes on persistent media. A set of the volumes can store at least one portion of a same copy of data. The method can further include caching the set of the volumes as a single group. In an embodiment, the plurality of volumes can include at least one of drives, snapshots, clones and replicas.Type: GrantFiled: September 29, 2014Date of Patent: August 14, 2018Assignee: Dell Products, LPInventors: Daniel E. Suman, Jason C. Shamberger, Lazarus J. Vekiarides
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Patent number: 10049051Abstract: Systems and methods are described to reserve cache space of points of presence (“POPs”) within a content delivery network (“CDN”). A provider may submit a request to the CDN to reserve cache space on one or more POPs for data objects designated by that provider. Thereafter, the CDN may mark those designated data objects within its cache as protected from eviction. When the CDN implements a cache eviction policy on the cache, the protected objects may be ignored for purposes of eviction, or may be evicted only after non-protected data objects.Type: GrantFiled: December 11, 2015Date of Patent: August 14, 2018Assignee: Amazon Technologies, Inc.Inventor: Matthew Graham Baldwin
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Patent number: 10042554Abstract: A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.Type: GrantFiled: November 19, 2015Date of Patent: August 7, 2018Assignee: International Business Machines CorporationInventors: Ekaterina M. Ambroladze, Garrett M. Drapala, Norbert Hagspiel, Sascha Junghans, Matthias Klein, Gary E. Strait
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Patent number: 10037285Abstract: The disclosed technology includes techniques for efficiently streaming media content from a multi-tiered storage system. An example implementation may be used for adaptive HTTP streaming of video segments and other content. In some implementations, flash memory SSDs (SLC or MLC) may form an intermediate cache layer between a first layer of DRAM cache and third layer of HDDs. Significant architectural elements of various implementations include optimal write granularity to overcome the write amplification effect of flash memory SSDs and a QoS-sensitive caching strategy that monitors the activity of the flash memory SSDs to ensure that video streaming performance is not hampered by the caching activity.Type: GrantFiled: January 14, 2015Date of Patent: July 31, 2018Assignee: Georgia Tech Research CorporationInventors: Umakishore Ramachandran, Mungyung Ryu
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Patent number: 10031690Abstract: The system, process, and methods herein describe a mechanism for creating an initial backup snapshot on deduplicated storage. Initialization IO's may be transmitted to the deduplicated storage, and those initialization IO's may be synthesized into a snapshot. Application IO's may also be transmitted in case the source side data changes while the backup is synthesized.Type: GrantFiled: December 16, 2013Date of Patent: July 24, 2018Assignee: EMC IP Holding Company LLCInventors: Anestis Panidis, Assaf Natanzon, Saar Cohen
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Patent number: 10025518Abstract: Methods and apparatus for obtaining property data for an object that is monitored for change, wherein the data source contains data for a current cycle. Further obtaining property data for the object for a previous cycle and comparing the property data for the object for the current and previous cycles to generate a change event when the property data for the object for the current and previous cycles do not match.Type: GrantFiled: September 30, 2014Date of Patent: July 17, 2018Assignee: EMC IP Holding Company LLCInventors: Vineeth Totappanavar, Santoshkumar Kavadimatti, Sameer Kumar Patro, Dominique Prunier, Afzal Rahman Jan
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Patent number: 9977734Abstract: According to one embodiment, an information processing device includes a nonvolatile memory, assignment unit, and transmission unit. The assignment unit assigns logical address spaces to spaces. Each of the spaces is assigned to at least one write management area included in a nonvolatile memory. The write management area is a unit of an area which manages the number of write. The transmission unit transmits a command for the nonvolatile memory and identification data of a space assigned to a logical address space corresponding to the command.Type: GrantFiled: March 12, 2015Date of Patent: May 22, 2018Assignee: Toshiba Memory CorporationInventors: Shinichi Kanno, Daisuke Hashimoto
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Patent number: 9971513Abstract: A method for caching a data block stored on a first storage device and onto a second storage device including determining whether a data block being requested contains a first type of data, upon a condition in which the data block contains the first type of data, writing the data block to the second storage device and upon a condition in which the data block does not contain the first type of data, determining whether a correspondingly mapped block on the second storage device contains the first type of data, and only writing the data block to the second storage device upon a condition in which the correspondingly mapped block does not contain the first type of data.Type: GrantFiled: July 24, 2012Date of Patent: May 15, 2018Assignee: INTEL CORPORATIONInventors: Angelos Bilas, Michail D. Flouris, Yannis Klonatos, Thanos Makatos, Manolis Marazakis
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Patent number: 9965196Abstract: Storage systems track free blocks using various data structures and maps. For instance, free block maps may contain data blocks with values that indicate whether a block is free or not. When an operation results in a block being freed, the relevant data block in the maps must be written during an I/O operation to update the value. Large numbers of updates my occur after an operation that frees a large numbers of blocks, which can lead to performance degradation. Accordingly, disclosed are systems and methods for deferring updating of free block data tracking structures using logs.Type: GrantFiled: October 20, 2014Date of Patent: May 8, 2018Assignee: NETAPP, INC.Inventors: Rohit Singh, Jungsook Yang, Rajesh Khandelwal, Jayalakshmi Pattabiraman
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Patent number: 9965189Abstract: A method includes, in a tape apparatus system, receiving a request to write a file from a host, and, in response to the request, dividing sequentially received data of the file into two or more segments. Each of the two or more segments have a predetermined size. The method further includes sequentially writing a series of the two or more segments onto one or more tapes, and determining the predetermined size based on a capacity use efficiency of a plurality of other tapes and a time to copy when a spanning file, written by spanning on the one or more tapes, is copied to the plurality of other tapes. A corresponding computer program product and computer system are also disclosed.Type: GrantFiled: September 10, 2015Date of Patent: May 8, 2018Assignee: International Business Machines CorporationInventors: Tohru Hasegawa, Masayuki Iwanaga, Yutaka Oishi
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Patent number: 9940069Abstract: A method, article of manufacture, apparatus, and system for a paging cache is disclosed. The backup cache may be broken into pages, and a subset of these pages may be memory resident. The pages may be sequentially loaded into memory to improve cache performance.Type: GrantFiled: February 27, 2013Date of Patent: April 10, 2018Assignee: EMC IP HOLDING COMPANY LLCInventors: Scott C. Auchmoody, Orit Levin-Michael, Scott H. Ogata
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Patent number: 9898218Abstract: An aspect includes determining a configuration change to at least one memory device of a memory system. A band switch enable command is sent from a memory controller to the at least one memory device indicating the configuration change. One or more internal circuits of the at least one memory device are set into a quiescent mode based on receiving the band enable command. One or more of a voltage and a frequency of the at least one memory device are adjusted to implement the configuration change. A band switch disable command is sent from the memory controller to the at least one memory device based on completing the adjusting. The one or more internal circuits are enabled to operate using the adjustment based on receiving the band switch disable command from the memory controller.Type: GrantFiled: February 5, 2016Date of Patent: February 20, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael B. Healy, Hillery C. Hunter, Kyu-hyoun Kim
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Patent number: 9891834Abstract: A method includes, in a tape apparatus system, receiving a request to write a file from a host, and, in response to the request, dividing sequentially received data of the file into two or more segments. Each of the two or more segments have a predetermined size. The method further includes sequentially writing a series of the two or more segments onto one or more tapes, and determining the predetermined size based on a capacity use efficiency of a plurality of other tapes and a time to copy when a spanning file, written by spanning on the one or more tapes, is copied to the plurality of other tapes. A corresponding computer program product and computer system are also disclosed.Type: GrantFiled: November 17, 2016Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Tohru Hasegawa, Masayuki Iwanaga, Yutaka Oishi
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Patent number: 9891980Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.Type: GrantFiled: December 29, 2011Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Boris Ginzburg, Ronny Ronen, Ilya Osadchiy
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Patent number: 9886383Abstract: A non-volatile storage system having Non-Volatile Memory (NVM) provides self-journaling and hierarchical consistency, enabling low-latency recovery and force unit access handshake. Mappings between host addresses and addresses in the NVM are maintained via one or more map entries, enabling locating of host data written to the NVM. Objects stored in the NVM include sufficient information to recover the object solely within the object itself. The NVM is managed as one or more data streams, a map stream, and a checkpoint stream. Host data is written to the data streams, map entries are written to the map stream, and checkpoints of map entries and other data structures are written to the checkpoint stream. Time markers embedded in the streams enable determination, during recovery, that selected portions of the streams are inconsistent with each other and are to be discarded.Type: GrantFiled: February 1, 2015Date of Patent: February 6, 2018Assignee: SEAGATE TECHNOLOGY LLCInventors: Earl T Cohen, Timothy L Canepa
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Patent number: 9880939Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a device controller, and a tag memory. The device controller stores a part of a logical-to-physical address translation table (L2P table) stored in the nonvolatile memory in a memory of a host as a cache. The tag memory includes a plurality of entries associated with a plurality of cache lines of the cache. Each entry includes a tag indicating which area of the L2P table is stored in a corresponding cache line, and a plurality of bitmap flags indicating whether a plurality of sub-lines included in the corresponding cache line are valid or not.Type: GrantFiled: February 5, 2016Date of Patent: January 30, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Konosuke Watanabe, Satoshi Kaburaki, Tetsuhiko Azuma
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Patent number: 9880907Abstract: In one embodiment, an apparatus comprises a processor and logic integrated with and/or executable by the processor, the logic being configured to cause the processor to receive, from a host, a command directed to a volume, the command including a parameter. The logic is further configured to cause the processor to evaluate a policy associated with the host, and, based on the evaluation of the policy associated with the host, determine a value of the parameter included in the command. Still yet, the logic is configured to cause the processor to open two copies of the volume in response to the parameter including a first value, and open only one of the two copies of the volume in response to the parameter including a second value.Type: GrantFiled: March 31, 2015Date of Patent: January 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erika M. Dawson, Katsuyoshi Katori, Takeshi Nohta, Joseph M. Swingler