Abstract: Example embodiments disclosed herein relate to hibernation. A device includes a non-volatile memory including a solid state memory and a volatile memory. The volatile memory includes a plurality of pages. One or more of the pages are caused to be stored to non-volatile memory based on whether the respective pages are sourced from the solid state memory.

Abstract: A system and method is disclosed for performing a backup of electronic data. An example method includes storing a first incremental data backup portion of a dataset in an electronic memory where the first incremental data backup includes both modified and unmodified portions of the dataset. Once stored, the method includes determining whether the first incremental data backup is a complete backup of the dataset. If the first incremental data backup is not a complete backup of the dataset, the method stores one or more additional incremental data backups of the dataset in the electronic memory that include additional modified and unmodified portions of the dataset until a full backup of the dataset is created.

Abstract: Provided is a memory mapping method, and particularly provided is a nonvolatile main memory mapping method for managing a nonvolatile main memory. The nonvolatile memory mapping method includes: performing a system call in order to access a file page that is required to operate a process stored in a kernel area of a nonvolatile main memory, wherein both the file page and process are stored in the kernel area of the nonvolatile main memory; and mapping a physical address of the file page to a virtual address of a user area of the nonvolatile main memory.

Abstract: A system and method for utilizing unmapped and unknown states in a storage system. When a first portion of a first medium is determined to be unreachable from any other mediums, the first portion of the first medium may be put into an unmapped state, and its data may be discarded and the corresponding storage locations may be freed. During replication of the first medium to a replica storage array, the state of the first portion of the first medium may be translated from the unmapped state into an unknown state on the replica storage array. If another storage array has the data of the first portion of the first medium, this data may be used to overwrite the first portion of the first medium on the replica storage array, converting the first portion of the first medium from the unknown state into the mapped state.

Abstract: A response reading method and a data transmission system are provided. The method includes, transmitting a first operation command sequence corresponding to a first temporary file to a memory storage device by a system, where the first operation command sequence instructs a smart card to execute a first operation. The method also includes, executing a first writing operation of a first dummy file to update first data in a cache memory. The method further includes, executing a response reading operation corresponding to a second temporary file by the system to read a response of the smart card corresponding to the first operation command sequence.

Abstract: A hardware and/or software facility to enable emulated storage devices to share data stored on physical storage resources of a storage system. The facility may be implemented on a virtual tape library (VTL) system configured to back up data sets that have a high level of redundancy on multiple virtual tapes. The facility organizes all or a portion of the physical storage resources according to a common store data layout. By enabling emulated storage devices to share data stored on physical storage resources, the facility enables deduplication across the emulated storage devices irrespective of the emulated storage device to which the data is or was originally written, thereby eliminating duplicate data on the physical storage resources and improving the storage consumption of the emulated storage devices on the physical storage resources.

Abstract: Methods, systems, and computer program products for providing reverse copy-on-write for improved cache utilization are disclosed. Examples generally relate to both physical and virtualized computer systems. A computer-implemented method may include detecting when a first task is to write to a memory page that is shared with a second task, creating a copy of the memory page for use by the second task, and modifying a memory mapping to associate the second task with the copy of the memory page. In a virtualized computer system, a hypervisor may detect when a first virtual machine is to write to a memory page shared with a second virtual machine, create a copy of the memory page for the second virtual machine, and adjust a memory mapping to associate the second virtual machine with the copy of the memory page.

Abstract: Address-based thresholds for freemained frames are used to determine retention actions. Based, at least in part, on a comparison of a number of freemained frames for an address space against a threshold of freemained frames for the address space, freemained frames can be retained or rejected and/or the threshold can be adjusted.

Abstract: An electronic counter is provided having a sequence of memory cells and increment logic. Each memory cell of the sequence is non-volatile and supports a one state and a zero state. The one state can also be referred to as a ‘programmed state’, the zero state as an ‘erased state’. The counter is configured to represent at least part of a current counting-state of the counter as a pattern of one and zero states in the memory cells of the sequence of memory cells, and increment logic configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter.

Abstract: A computer-implemented method is disclosed in which a memory suballocation application obtains, from an underlying memory allocation system (UMAS), allocation of a plurality of cell blocks. Each cell block includes a plurality of equally-sized cells and a bitmap indicating which of its cells are available. A request is received from a requesting application for dynamic allocation of a given amount of memory. If the given amount of memory exceeds a maximum cell size, memory allocation is initiated via the UMAS for the given amount of memory without using the cell blocks. If the given amount of memory does not exceed the maximum cell size, a desired cell size is determined. If a bitmap of one of the cell blocks indicates that a cell having the desired cell size is available, the memory suballocation application is used to dynamically allocate a cell having the desired cell size to the requesting application.

Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.

Abstract: An asynchronous FIFO buffer that provides data in response to requests to read a memory array is disclosed. The asynchronous FIFO buffer provides the data output within a latency tolerance. The asynchronous FIFO has a read clock input and a write clock input. The read clock input receives a read enable signal that defines how data should be clocked out. The write clock input receives a write clock that is asynchronous from the read enable signal. The asynchronous FIFO inputs data from the memory array in accordance with the write clock signal. The asynchronous FIFO outputs data in accordance with the read enable signal. Control logic may pre-fetch data from the memory array into the asynchronous FIFO prior to the read enable signal first being received.

Abstract: The disclosure generally relates to methods and systems for application level caching and more particularly to dynamically applying caching policies to a software application. In one embodiment, an application level caching method, comprising: monitoring, using a utility executed by a processor, run-time data access operations corresponding to an application; identifying, using the processor, at least one characteristic associated with the run-time data access operations; triggering, using the processor, a caching rule based on the at least one characteristic associated with the run-time data access operations; and providing, using the processor, a memory access instruction according to the caching rule.

Abstract: Provided are a computer program product, system, and method for establishing a point-in-time copy relationship between source logical addresses and target logical addresses. A point-in-time (PiT) copy establish command specifies a source set comprising a subset of source logical addresses in at least one storage and a target set comprising a subset of target logical addresses in the at least one storage. The source set of source logical addresses are copied to the target set of target logical addresses. The source logical addresses map to source tracks and wherein the target logical addresses map to target tracks. Copy information is generated indicating whether the source logical addresses in the source set have been copied to the target set. Complete is returned to the PiT copy establish command after generating the copy information and before copying all the source logical addresses to the target logical addresses.

Abstract: A system and method is described that accesses a network persistent memory unit (nPMU). One embodiment comprises a primary region corresponding to a predefined portion of a primary network persistent memory unit (nPMU) communicatively coupled to at least one client processor node via a communication system, wherein the primary region is assigned to a client process running on the client processor node and is configured to store information received from the client process; and a mirror region corresponding to a predefined portion of a mirror nPMU communicatively coupled to the client processor node via the communication system, wherein the mirror region is assigned to the client process and is configured to store the information received from the client process.

Abstract: In some embodiments, in response to execution of a load-reserve instruction that binds to a load target address held in a store-through upper level cache, a processor core sets a core reservation flag, transmits a load-reserve operation to a store-in lower level cache, and tracks, during a core reservation tracking interval, the reservation requested by the load-reserve operation until the store-in lower level cache signals that the store-in lower level cache has assumed responsibility for tracking the reservation. In response to receipt during the core reservation tracking interval of an invalidation signal indicating presence of a conflicting snooped operation, the processor core cancels the reservation by resetting the core reservation flag and fails a subsequent store-conditional operation.

Abstract: The present invention provides a method and apparatus for data swap in a virtual machine environment. The present invention provides a method for data swap in a virtual machine environment, including: in response to a swap request from a virtual machine, looking up storage space associated with the swap request; and allocating to the virtual machine free physical storage space, in a host, which matches the storage space, so that the free physical storage space logically becomes available storage space to the virtual machine; the virtual machine is running on the host, and the storage space is physical storage space in the host.

Abstract: In some embodiments, in response to execution of a load-reserve instruction that binds to a load target address held in a store-through upper level cache, a processor core sets a core reservation flag, transmits a load-reserve operation to a store-in lower level cache, and tracks, during a core reservation tracking interval, the reservation requested by the load-reserve operation until the store-in lower level cache signals that the store-in lower level cache has assumed responsibility for tracking the reservation. In response to receipt during the core reservation tracking interval of an invalidation signal indicating presence of a conflicting snooped operation, the processor core cancels the reservation by resetting the core reservation flag and fails a subsequent store-conditional operation.

Abstract: A data writing method for a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same are provided. The method includes partitioning physical blocks of the rewritable non-volatile memory module into a data area and a spare area and configuring logical blocks. The method also includes selecting physical blocks from the spare area as spare physical blocks corresponding to a logical block and using only lower physical pages of the spare physical blocks to store updated data that is to be written into the logical block. The method further includes moving valid data of all logical pages of the logical block into a physical block of the data area, wherein each lower physical page and an upper physical page corresponding thereto in the physical block are programmed together. Accordingly, the method can effectively improve the speed and reliability of writing data.

Abstract: A level of cache memory receives modified data from a higher level of cache memory. A set of cache lines with an index associated with the modified data is identified. The modified data is stored in the set in a cache line with an eviction priority that is at least as high as an eviction priority, before the modified data is stored, of an unmodified cache line with a highest eviction priority among unmodified cache lines in the set.