Abstract: A system can comprise an I/O circuitry, a processor, reconfigurable circuitry, an array of flash storage devices, and a serial interconnect network that is coupled to transfer data between the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The processor can be configured to designate an interconnect address space for use in communication over the interconnect network among the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The reconfigurable circuitry can be configured to translate data addresses during transfers of data between the I/O circuitry and the array of flash storage devices. A method to access an array of flash storage devices that are coupled to I/O circuitry over a serial interconnect network can comprise using reconfigurable circuitry to capture data during transfers of data over the serial interconnect network.

Abstract: A method, system, and computer readable storage medium for providing data to a user interface for performance monitoring are disclosed, in which an a data definition is acquired, where the data definition is generated in response to a definition of the user interface. Data is acquired from data sources based on the data definition. The acquired data is processed based on the data definition, and the processed data is cached.

Abstract: Address-based thresholds for freemained frames are used to determine retention actions. Based, at least in part, on a comparison of a number of freemained frames for an address space against a threshold of freemained frames for the address space, freemained frames can be retained or rejected and/or the threshold can be adjusted.

Abstract: Provided are a computer program product, system, and method for managing updates and copying data in a point-in-time copy relationship expressed as source logical addresses and target logical addresses. A copy relationship indicates a source set of a subset of source logical addresses to copy to a target set comprising a subset of target logical addresses. An update is received to a source logical address that has not been copied. Determinations are made of the target logical address corresponding to the source logical address to be updated according to the copy relationship, a target group of target logical addresses in the target set that include the determined target logical address, and the source logical addresses in the source set that correspond to the target logical addresses in the target group. The determined source logical addresses are copied to the target logical addresses in the determined target group.

Abstract: Embodiments of the approaches disclosed herein include a subsystem that includes an access tracking mechanism configured to monitor access operations directed to a first memory and a second memory. The access tracking mechanism detects an access operation generated by a processor for accessing a first memory page residing on the second memory. The access tracking mechanism further determines that the first memory page is included in a first subset of memory pages residing on the second memory. The access tracking mechanism further locates, within a reference vector, a reference bit that corresponds to the first memory page, and sets the reference bit. One advantage of the present invention is that memory pages in a hybrid system migrate as needed to increase overall memory performance.

Abstract: A portion of a reprogrammable storage device is used to implement permanent data storage. The storage device includes a plurality of electrically erasable memory elements and a controller. The plurality of electrically erasable memory elements are configured to store data. Each memory element is programmable a number of write cycles before reaching a write failure state. The controller is coupled to the plurality of memory elements. The controller includes a receiver and a write engine. The receiver receives an instruction to drive a selected memory element to the write failure state. The write engine repeatedly writes a data value, in a plurality of write operations, to the selected memory element until the write failure state of the selected memory element is established.

Abstract: Embodiments relate to implementing a coherence protocol. An aspect includes sending a request for data to a remote processor and receiving by a processor a response from the remote processor. The response has a transaction status of a remote transaction on the remote processor. The processor adds the transaction status of the remote transaction on the remote processor in a local transaction interference tracking table.

Abstract: Disclosed aspects include managing the access of flash memory by a computer system. A physical memory address space which includes a flash memory portion is established. The flash memory portion may correspond to an input/output memory range. An access request may be detected with respect to the physical memory address space. Using a load-store technique to process the access request, the flash memory portion of the physical memory address space may be accessed.

Abstract: Disclosed aspects include managing the access of flash memory by a computer system. A physical memory address space which includes a flash memory portion is established. The flash memory portion may correspond to an input/output memory range. An access request may be detected with respect to the physical memory address space. Using a load-store technique to process the access request, the flash memory portion of the physical memory address space may be accessed.

Abstract: A mobile electronic device including an interface unit, a semiconductor storage device and a processor is provided. The interface unit provides a user interface to receive a user input. The semiconductor storage device includes a controller and a non-volatile memory. The non-volatile memory is coupled to the controller and includes a plurality of memory blocks. The processor is coupled to the interface unit and the semiconductor storage device. The processor sends a signal to the semiconductor storage device in response to the user input. The controller clears at least one of the memory blocks in response to the signal.

Abstract: A system is provided that includes a remote device and bus controller coupled to the remote device via a digital network bus. The remote device includes one or more data channels for respective one or more peripherals, and includes volatile channel-based memory for each data channel and non-volatile device-based memory for the remote device. The bus controller is and configured to send a command across the network bus to the remote device, and in response thereto, the remote device is configured to acquire data from a designated data channel or command the designated data channel to perform a conversion. The command is from a communication protocol with which the remote device is compatible, and includes a set of channel commands for accessing the channel-based memory, and a different, distinct set of device-memory commands for accessing the device-based memory. The channel commands and device-memory commands have different timing requirements.

Abstract: An interface receives a command corresponding to a non-volatile memory. The interface determines whether a bypass mode is enabled and whether the command is a medium-access command. A primary processing node processes the command in response to determining at least one of the following: that the bypass mode is disabled or that the command is not a medium-access command. A secondary processing node processes the command, in response to determining that the bypass mode is enabled and that the command is a medium-access command.

Abstract: A system according to one embodiment includes non-volatile memory, and a non-volatile memory controller having a cache. An architecture of the cache supports separation of data streams, and the cache architecture supports parallel writes to different non-volatile memory channels. Additionally, the cache architecture supports pipelining of the parallel writes to different non-volatile memory planes. Furthermore, the non-volatile memory controller is configured to perform a direct memory lookup in the cache based on a physical block address. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A data storing method for storing data in a rewritable non-volatile memory module is provided. The method includes temporarily storing first data into a buffer memory; and starting a flush operation to write the first data from the buffer memory into a first physical programming unit. The method further includes determining whether the first physical programming unit is a lower physical programming unit; and if yes, writing second data into a second physical programming unit, wherein the second physical programming unit belongs to an upper physical programming unit, and the second physical programming unit and the first physical programming unit are formed by the same memory cells disposed on the same word line. Accordingly, the method can effectively prevent the data written during the flush operation from losing due to the programming fail occurred on other physical programming units.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed. A method includes tracking which portions of data stored in a volatile memory buffer are not yet stored in a non-volatile memory medium. A volatile memory buffer may be accessible using memory semantics. A volatile memory buffer may be associated with logic configured to ensure that the data stored in the volatile memory buffer is non-volatile. A method includes maintaining consistency of data between a volatile memory buffer and a non-volatile memory medium based on tracked portions of the data. A method includes copying at least portions of data not yet stored in a non-volatile memory medium to the non-volatile memory medium in response to a trigger.

Abstract: Systems, methods, and computer program products for mirroring dual writeable storage arrays are provided. Various embodiments provide configurations including two or more mirrored storage arrays that are each capable of being written to by different hosts. When commands to write data to corresponding mirrored data blocks within the respective storage arrays are received from different hosts at substantially the same time, write priority for writing data to the mirrored data blocks is given to one of the storage arrays based on a predetermined criterion or multiple predetermined criteria.

Abstract: A method of writing data to a range of logical blocks in a storage medium includes: receiving a command including a starting logical block address, a value indicating a range of logical block addresses to be written, and a logical block of data; storing the logical block in a first temporary storage; generating a logical page by duplicating the logical block a plurality of times corresponding to a number of logical blocks in a logical page and transporting the generated logical page to a second temporary storage and storing the generated logical page in the second temporary storage; writing the generated logical page from the second temporary storage into the storage medium beginning from the starting logical block address; and performing a read-modify-write operation if the first write operation does not begin on a logical page boundary or the last write operation does not end on a logical page boundary.

Abstract: Provided are a computer program product, system, and method for deduplicating chunk digests received for chunks in objects in objects provided by clients to store in a storage. An index has chunk signatures calculated from chunks of data in the data objects in the storage. A transaction requests a shared lock for a chunk digest calculated from a chunk in an object to add to the storage. In response to not receiving the shared lock, the transaction is granted a shared lock to the chunk digest in wait mode. The transaction does not proceed until being granted the shared lock. In response to receiving the shared lock, a determination is made as to whether the chunk digest is in the index. A reference to the chunk data is provided for the object when the chunk digest is indicated in the index.

Abstract: A system and method for combining the execution of a query with other operations, such as a data retention scan, in a storage device, when the execution of the query is not time-sensitive. The storage device may be connected to a host, and may operate during intervals of time in a power save mode. When a query is received by the host that is not time-sensitive, the query may be stored in the host or in the storage device until such time as the device would otherwise return to a normal operating mode, and then the query may be executed. Such delayed execution may enable the sharing of read operations for the query with read operations used, for example, for the execution of other queries or for a data retention scan.

Abstract: Provided are a computer program product, system, and method for processing a copy command indicating a source set comprising a subset of source logical addresses to copy to an indicated target set comprising a subset of target logical addresses. Complete is expected to be returned to the copy command in response to completing the copying of the source set to the target set. A point-in-time (PiT) copy establish command is generated in response to receiving the copy command, indicating the source and target sets in the copy command, The generated PiT copy command is executed to generate copy information indicating the source and target sets of source logical addresses and whether they have been copied to the target set. Complete is returned to the copy command after generating the copy information and before copying all the source logical addresses to the target logical addresses.