Abstract: The inventions disclosed herein provide a crash-proof cache data protection method and system. The cache data backup steps include: when power interruption unexpectedly occur, a preselected central processing unit receiving an interrupt request signal; querying to obtain index nodes of block devices corresponding to logical volume management volumes; according to the index nodes, acquiring a page needing to be stored in a flash memory; acquiring a buffer head in the page, and storing information of the buffer head and buffer data corresponding to the buffer head into the flash memory, and generating backup data.

Abstract: An information processing device includes a processor. The processor is configured to transmit to a tape drive a write request in one of a first mode and a second mode for accompanying data. The write request in the first mode requests to store the accompanying data in a buffer memory included in the tape drive without writing the accompanying data to a magnetic tape. The write request in the second mode requests to write data stored in the buffer memory and the accompanying data to the magnetic tape. The processor is configured to transmit a write request for one of multiple pieces of data in the first mode if a remaining amount of the buffer memory is larger than a predetermined threshold value, and in the second mode if the remaining amount is equal to or smaller than the predetermined threshold value.

Abstract: Provided are a computer program product, system, and method for establishing a point-in-time copy relationship between source logical addresses and target logical addresses. A point-in-time (PiT) copy establish command specifies a source set comprising a subset of source logical addresses in at least one storage and a target set comprising a subset of target logical addresses in the at least one storage. The source set of source logical addresses are copied to the target set of target logical addresses. The source logical addresses map to source tracks and wherein the target logical addresses map to target tracks. Copy information is generated indicating whether the source logical addresses in the source set have been copied to the target set. Complete is returned to the PiT copy establish command after generating the copy information and before copying all the source logical addresses to the target logical addresses.

Abstract: A memory device includes a memory component that store data and a processor. The processor may generate one or more data packets associated with the memory component. Each data packet may include a transaction type field that includes data indicative of a first size of a payload of the respective data packet and a second size of an error control code in the respective data packet. Each packet may also have a payload field that includes the payload and an error control code field that includes the error control code. The processor may transmit the data packets to a requesting component, such that the requesting component identifies the payload field and the error control field of each data packet based on the data of the transaction type field in each data packet.

Abstract: A method for writing data objects, the method may include accumulating, in a first memory module, multiple new data entities in one or more dirty pages of a data layer; wherein each new data entity and a corresponding older data entity are associated with a same application object; wherein the accumulating comprises storing each new data entity in a page that differs from a page that stores the corresponding older data entity; calculating multiple new sets of descriptors by generating to each new data entity, a new set of descriptors; wherein each set of descriptors comprises descriptors that belong to multiple descriptors layers; wherein the multiple descriptors layers and the data layer belong to an hierarchical data structure; accumulating the multiple new sets of descriptors in one or more dirty pages of one or more descriptors layers; wherein each corresponding older data entity is associated with a corresponding set of descriptors; wherein the accumulating comprises storing each new set of descriptor in

Abstract: A hypervisor detects a page fault associated with the request for a device assigned to a guest operating system to perform direct memory access (DMA) of a requested page of memory, invalidates a mapping in a central processing unit (CPU) page table of a guest physical address to a host physical address for a candidate page for being swapped out of host memory, checks a DMA access state of the candidate page to determine whether or not the candidate page can be swapped out from the host memory, and removes the candidate page from the host memory in response to determining that the DMA access state indicates that the candidate page can be swapped out.

Abstract: An information handling system includes a processor having a plurality of memory channels. The information handling system also includes a plurality of dual inline memory modules non-symmetrically populated on the memory channels. The dual inline memory modules are divided by bank to create a plurality of interleave groups, and each of the interleave groups spans across all of the memory channels of the processor.

Abstract: Methods of operating a memory device are useful in managing wear leveling operations. Such methods include receiving an instruction from a host device in communication with the memory device, wherein the instruction comprises a command portion indicating a desire to identify portions of the memory device to be excluded from wear leveling operations and an argument portion comprising information identifying a particular group of one or more blocks of the plurality of blocks; storing the information identifying the particular group of one or more blocks to a non-volatile memory of the memory device as a portion of information identifying blocks to be excluded from wear leveling operations; and performing one or more wear leveling operations only on a subset of the plurality of blocks responsive to the information identifying blocks to be excluded from wear leveling operation.

Abstract: A memory protection module includes comparison logic that has a write-once window CSR that stores a memory address range, and window protection logic. The comparison logic receives a memory write transaction, determines a memory address of the memory write transaction, and provides an indication as to whether or not the memory address is included in the memory address range. The window protection logic receives the memory transaction, receives the indication from the comparison logic, allows the memory write transaction to proceed in response to the indication indicating that the memory address is not included in the memory address range, and drops the memory write transaction in response to the indication indicating that the memory address is included in the memory address range.

Abstract: A writing method of a storage system which includes a host and a storage connected to the host, includes receiving journal data during a generation of a data writing transaction; inserting in a first map table, a plurality of entries, each entry including a first logical address of a first logical area of the storage and a second logical address of a second logical area of the storage; writing the journal data to a physical area of the storage corresponding to the first logical address; and remapping the physical area from the first logical address onto the second logical address using the plurality of entries when a size of a usable space of the first logical area is less than a desired value.

Abstract: A processor uses a token scheme to govern the maximum number of memory access requests each of a set of processor cores can have pending at a northbridge of the processor. To implement the scheme, the northbridge issues a minimum number of tokens to each of the processor cores and keeps a number of tokens in reserve. In response to determining that a given processor core is generating a high level of memory access activity the northbridge issues some of the reserve tokens to the processor core. The processor core returns the reserve tokens to the northbridge in response to determining that it is not likely to continue to generate the high number of memory access requests, so that the reserve tokens are available to issue to another processor core.

Abstract: Aspects of the subject matter described herein relate to storage systems and aliased memory. In aspects, a file system driver or other component may send a request to a memory controller to create an alias between two blocks of memory. One of the blocks of memory may be used for main memory while the other of the blocks of memory may be used for a storage system. In response, the memory controller may create an alias between the blocks of memory. Until the alias is severed, when the memory controller receives a request for data from the block in main memory, the memory controller may respond with data from the memory block used for the storage system. The memory controller may also implement other actions as described herein.

Abstract: Provided are a computer program product, system, and method for allocating additional requested storage space for a data set in a first managed space in a second managed space. A request for additional storage space is received for a requested data set stored in a first managed space in the storage. A revised amount of storage space for the requested data set comprises at least an amount of space currently allocated to the requested data set in the first managed space and the requested additional storage space. If the revised amount of storage space exceeds a value, then allocation is made of the revised amount of storage space in allocated storage space in a second managed space of the storage. The data set is stored in the allocated storage space in the second managed space.

Abstract: Provided are a computer program product, system, and method for allocating additional requested storage space for a data set in a first managed space in a second managed space. A request for additional storage space is received for a requested data set stored in a first managed space in the storage. A revised amount of storage space for the requested data set comprises at least an amount of space currently allocated to the requested data set in the first managed space and the requested additional storage space. If the revised amount of storage space exceeds a value, then allocation is made of the revised amount of storage space in allocated storage space in a second managed space of the storage. The data set is stored in the allocated storage space in the second managed space.

Abstract: In one aspect, a device includes a processor, memory accessible to the processor, and storage accessible to the processor. The storage bears instructions executable by the processor to determine a context associated with the device and at least in part based on the determination, configure a standby portion of the memory.

Abstract: A computer-implemented method for protecting virtual machine data may include (1) receiving a request to perform a granular backup operation on data stored by a guest system within a virtual machine, (2) identifying a storage container that comprises an agent that performs backup operations, (3) attaching the storage container to the virtual machine in response to the request, and (4) performing the granular backup operation by sending an instruction to the guest system within the virtual machine to execute the agent. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A buffer memory management method, a memory control circuit unit and a memory storage device are provided. The buffer memory management method includes allocating a mapping table zone having a first zone and a second zone in the buffer memory, and temporarily storing a plurality of logical address-physical address mapping tables into the first zone and the second zone, and receiving a first write command which indicates writing first data into a first logical address. A first logical address-physical address mapping table to which the first logical address belongs is temporarily stored into a first buffer unit in the second zone. The method also includes updating the first logical address-physical address mapping table, moving the updated first logical address-physical address mapping table into a second buffer unit in the first zone, and marking the second buffer unit as a dirty status.

Abstract: Commands associated with one or more logical block addresses are received via a host interface of a storage device. Based on a timing and sequence of the commands, an extent of a file that contains the logical block addresses is determined, the file being stored on the storage device. The logical block addresses are managed internally as a unitary data structure based on determining an association between the logical block addresses and the file.

Abstract: In some embodiments, a method for controlling a cache having a volatile memory and a non-volatile memory during a power up sequence is provided. The method includes receiving, at a controller configured to control the cache and a storage device associated with the cache, a signal indicating whether the non-volatile memory includes dirty data copied from the volatile memory to the non-volatile memory during a power down sequence, the dirty data including data that has not been stored in the storage device. In response to the received signal, the dirty data is restored from the non-volatile memory to the volatile memory, and flushed from the volatile memory to the storage device.

Abstract: Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.