Patents Examined by Daniel Whalen
  • Patent number: 11561192
    Abstract: An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: January 24, 2023
    Assignee: Regents of the University of Minnesota
    Inventor: Steven J. Koester
  • Patent number: 11563031
    Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and distal regions proximate the control gate regions. The control gate regions have front surfaces, top surfaces and bottom surfaces. The top and bottoms surfaces extend back from the front surfaces. High-k dielectric material is along the control gate regions. The high-k dielectric material has first regions along the top and bottom surfaces, and has second regions along the front surfaces. The first regions are thicker than the second regions. Charge-blocking material is adjacent to the second regions of the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. Gate-dielectric material is adjacent to the charge-storage material. Channel material is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shyam Surthi, Richard J. Hill
  • Patent number: 11557722
    Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: January 17, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
  • Patent number: 11557664
    Abstract: A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: January 17, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Takayuki Tsutsui, Satoshi Tanaka
  • Patent number: 11552120
    Abstract: A chip-scale sensor package structure includes a sensor chip, a first package body surrounding and connected to an outer lateral side of the sensor chip, a ring-shaped support disposed on a top side of the first package body, a light permeable member disposed on the ring-shaped support, and a redistribution layer (RDL) disposed on a bottom surface of the sensor chip and a bottom side of the first package body. The sensor chip includes a sensing region arranged on the top surface thereof, a plurality of internal contacts, and a plurality of conductive paths respectively connected to the internal contacts and electrically coupled to the sensing region. The sensing region is spaced apart from the ring-shaped support by a distance less than 300 ?m. A bottom surface of the RDL has a plurality of external contacts electrically coupled to the internal contacts.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: January 10, 2023
    Assignee: KINGPAK TECHNOLOGY INC.
    Inventors: Fu-Chou Liu, Chien-Chen Lee, Li-Chun Hung, Ya-Han Chang
  • Patent number: 11539032
    Abstract: An organic light emitting diode and a manufacturing method thereof, a display panel are provided. The organic light emitting diode includes a light emitting structure and a first electrode structure. The first electrode structure is configured to drive the light emitting structure to emit light and includes a first electrode and a light reflecting layer, the light reflecting layer is disposed on a side of the first electrode away from the light emitting structure, wherein the first electrode and at least a portion of the light reflecting layer are overlapped with each other in a first direction, an insulating layer is at least partially disposed between the at least part of the light reflecting layer and the first electrode overlapped with each other, and the first direction is perpendicular to a plane on which the light reflecting layer is located.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: December 27, 2022
    Assignee: Beijing BOE Technology Development Co., Ltd.
    Inventors: Zhen Song, Guoying Wang
  • Patent number: 11527718
    Abstract: A mask assembly and an organic light emitting display device manufactured using the mask assembly are capable of realizing an organic light emitting display device having a hole in a display area, the mask assembly including a frame defining a first opening area, a first mask on the frame and defining a plurality of second opening areas that overlap the first opening area, and a second mask fixed to the frame across the plurality of second opening areas, and including a body portion overlapping the first mask, a blocking portion at each respective one of the second opening areas, and a pattern portion between the body portion and the blocking portion, and defining a plurality of holes.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: December 13, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sungwoo Jung, Soonjung Wang
  • Patent number: 11521966
    Abstract: A stacked three dimensional semiconductor device includes multiple thin substrates stacked over one another and over a base substrate. The thin substrates may include a thickness of about 0.1 ?m. In some embodiments, a noise suppression tier is vertically interposed between active device tiers. In some embodiments, each tier includes active device portions and noise suppression portions and the tiers are arranged such that noise suppression portions are vertically interposed between active device portions. The noise suppression portions include decoupling capacitors in a power/ground mesh and alleviate vertical noise.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shu-Chun Yang
  • Patent number: 11522145
    Abstract: A method for manufacturing a transistor being a bottom-gate transistor is provided. The method for manufacturing a transistor includes a step of forming a first metal layer 32 on an insulator layer 20 provided on a substrate 10 including a gate electrode, a step of applying a resist onto the first metal layer 32, and patterning the first metal layer 32 by a photolithographic method, an oxide film removal step of removing an oxide film 26 formed on the patterned first metal layer 32, and a step of forming a source electrode and a drain electrode by forming a second metal layer 42 on the first metal layer 32.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: December 6, 2022
    Assignee: NIKON CORPORATION
    Inventor: Shohei Koizumi
  • Patent number: 11522166
    Abstract: Embodiments of the present disclosure provide a display panel and an electronic device. The display panel includes: a back plate; a light emitting element on a side of the back plate; a circular polarizer on a side of the light emitting element away from the back plate; a wave plate on a side of the polarizer away from the back plate; and an anti-glare film layer on a side of the wave plate away from the back plate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: December 6, 2022
    Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventor: Mingche Hsieh
  • Patent number: 11508776
    Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: November 22, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Larry Kinsman, Yusheng Lin, Yu-Te Hsieh, Oswald Skeete, Weng-Jin Wu, Chi-Yao Kuo
  • Patent number: 11508852
    Abstract: A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; a gate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: November 22, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11508581
    Abstract: Plural sessions of proton irradiation are performed by differing ranges from a substrate rear surface side. After first to fourth n-type layers of differing depths are formed, the protons are activated. Next, helium is irradiated to a position deeper than the ranges of the proton irradiation from the substrate rear surface, introducing lattice defects. When the amount of lattice defects is adjusted by heat treatment, protons not activated in a fourth n-type layer are diffused, forming a fifth n-type layer contacting an anode side of the fourth n-type layer and having a carrier concentration distribution that decreases toward the anode side by a more gradual slope than that of the fourth n-type layer. The fifth n-type layer that includes protons and helium and the first to fourth n-type layers that include protons constitute an n-type FS layer. Thus, a semiconductor device having improved reliability and lower cost may be provided.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: November 22, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kouji Mukai, Souichi Yoshida
  • Patent number: 11502266
    Abstract: Alight-emitting element includes an anode electrode, a cathode electrode, a light-emitting layer, a positive hole transport layer, and an electron transport layer. The light-emitting layer, the positive hole transport layer, and the electron transport layer are provided between the anode electrode and the cathode electrode. The light-emitting layer includes QD phosphor particles, a positive hole transport substance configured to transport positive holes transported thereto by the positive hole transport layer, an electron transport substance configured to transport electrons transported thereto by the electron transport layer, and a photosensitive host material.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: November 15, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tokiyoshi Umeda, Yuto Tsukamoto, Masayuki Kanehiro, Youhei Nakanishi
  • Patent number: 11498831
    Abstract: A packaged micro-electro-mechanical system (MEMS) device (100) comprises a circuitry chip (101) attached to the pad (110) of a substrate with leads (111), and a MEMS (150) vertically attached to the chip surface by a layer (140) of low modulus silicone compound. On the chip surface, the MEMS device is surrounded by a polyimide ring (130) with a surface phobic to silicone compounds. A dome-shaped glob (160) of cured low modulus silicone material covers the MEMS and the MEMS terminal bonding wire spans (180); the glob is restricted to the chip surface area inside the polyimide ring and has a surface non-adhesive to epoxy-based molding compounds. A package (190) of polymeric molding compound encapsulates the vertical assembly of the glob embedding the MEMS, the circuitry chip, and portions of the substrate; the molding compound is non-adhering to the glob surface yet adhering to all other surfaces.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: November 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kurt Peter Wachtler, Makoto Yoshino, Ayumu Kuroda, Brian E. Goodlin, Karen Kirmse, Benjamin Cook, Genki Yano, Stuart Jacobsen
  • Patent number: 11495545
    Abstract: A semiconductor package includes an outer redistributed line (RDL) structure, a first semiconductor chip disposed on the outer RDL structure, a stack module stacked on the first semiconductor chip, and a bridge die stacked on the outer RDL structure. A portion of the stack module laterally protrudes from a side surface of the first semiconductor chip. The bridge die supports the protruding portion of the stack module. The stack module includes an inner RDL structure, a second semiconductor chip disposed on the inner RDL structure, a capacitor die disposed on the inner RDL structure, and an inner encapsulant. The capacitor die acts as a decoupling capacitor of the second semiconductor chip.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: November 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Jong Hoon Kim, Ki Jun Sung, Ki Bum Kim
  • Patent number: 11495778
    Abstract: A light emitting diode of an embodiment of the present disclosure includes a first electrode, a hole transport region on an upper portion of the first electrode and having a first refractive index, an emission layer on an upper portion of the hole transport region and having a second refractive index less than the first refractive index, an electron transport region on an upper portion of the emission layer, and a second electrode on an upper portion of the electron transport region.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: November 8, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bora Lee, Hyomin Ko
  • Patent number: 11476256
    Abstract: Some embodiments include an integrated assembly having a semiconductor-containing structure with a body region vertically between an upper region and a lower region. The upper region includes a first source/drain region. The lower region is split into two legs which are both joined to the body region. One of the legs includes a second source/drain region and the other of the legs includes a body contact region. The first and second source/drain regions are of a first conductivity type, and the body contact region is of a second conductivity type which is opposite to the first conductivity type. An insulative material is adjacent to the body region. A conductive gate is adjacent to the insulative material. A transistor includes the semiconductor-containing structure, the conductive gate and the insulative material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 11476385
    Abstract: Provided is an optical device including an active layer, which includes two outer barriers and a coupled quantum well between the two outer barriers. The coupled quantum well includes a first quantum well layer, a second quantum well layer, a third quantum well layer, a first coupling barrier between the first quantum well layer and the second quantum well layer, and a second coupling barrier between the second quantum well layer and the third quantum well layer. The second quantum well layer is between the first quantum well layer and the third quantum well layer. An energy band gap of the second quantum well layer is less than an energy band gap of the first quantum well layer, and an energy band gap of the third quantum well layer is equal to or less than the energy band gap of the second quantum well layer.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: October 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byunghoon Na, Changyoung Park, Yonghwa Park
  • Patent number: 11476207
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 18, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jian-Hsing Lee, Shao-Chang Huang, Chih-Hsuan Lin, Yu-Kai Wang, Karuna Nidhi, Hwa-Chyi Chiou