Patents Examined by Daniel Whalen
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Patent number: 12219845Abstract: A display apparatus includes: a substrate having a plurality of first group areas spaced apart from each other; a first pixel electrode and a second pixel electrode in each of the plurality of first group areas; a first intermediate layer on the first pixel electrode; a second intermediate layer on the second pixel electrode; an opposite electrode on the first intermediate layer and the second intermediate layer; and a plurality of first capping layers on the opposite electrode and spaced apart from each other to correspond to the plurality of first group areas.Type: GrantFiled: December 7, 2021Date of Patent: February 4, 2025Assignee: Samsung Display Co., Ltd.Inventors: Sanghoon Kim, Jongsung Park, Sangmin Yi, Sangshin Lee, Seungjin Lee, Eunjoung Jung
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Patent number: 12209214Abstract: A light-emitting element includes a hole transport layer between a light-emitting layer and an anode, the hole transport layer containing either a metal oxide of (NiO)1-x(LaNiO3)x (composition formula 1) or (CuyO)1-x(LaNiO3)x (composition formula 2), where 0<x?1 and 1?y?2.Type: GrantFiled: June 24, 2019Date of Patent: January 28, 2025Assignee: SHARP KABUSHIKI KAISHAInventors: Shinichi Handa, Yoshihiro Ueta, Noboru Iwata
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Patent number: 12213298Abstract: Transistors (N3, N4) corresponding to a drive transistor (PD1), transistors (N5, N6) corresponding to a drive transistor (PD2), transistors (N7, N8) corresponding to an access transistor (PG1), and transistors (N1, N2) corresponding to an access transistor (PG2) are formed in a lower portion of a cell. Transistors (P1, P2) corresponding to load transistors (PU1, PU2), respectively, are formed in an upper portion of the cell. Further, the transistors (P1, P2) overlap the transistors (N3, N6) in plan view.Type: GrantFiled: December 20, 2021Date of Patent: January 28, 2025Assignee: SOCIONEXT INC.Inventor: Masanobu Hirose
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Patent number: 12207531Abstract: The method of manufacturing a display device includes preparing a substrate having a first and second area surrounding a portion of the first area, forming a semiconductor layer in the first area, forming a first insulating layer covering the semiconductor layer, forming a gate electrode layer that at least partially overlaps the semiconductor layer, forming a pad electrode layer in the second area, forming a second insulating layer covering the gate electrode layer, forming contact holes that at least partially expose the semiconductor layer and the gate electrode layer, and forming a conductive layer positioned in the contact holes and including a first and second layer. The forming of the conductive layer includes forming a first layer material and a second layer material, and removing a portion of the first layer material and a portion of the second layer material to expose the second insulating layer.Type: GrantFiled: October 20, 2021Date of Patent: January 21, 2025Assignee: Samsung Display Co., Ltd.Inventors: Seungbae Kang, Heesung Yang, Byoungkwon Choo, Woojin Cho
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Patent number: 12198997Abstract: A semiconductor package includes an upper structure including a semiconductor chip and a first molding layer for molding the semiconductor chip, a lower structure provided on the upper structure, the lower structure including a conductive post and a second molding layer for molding the conductive post, and a redistribution structure provided between the upper structure and the lower structure, the redistribution structure including a wiring pattern for electrically connecting a pad of the semiconductor chip to the conductive post, in which a thermal expansion coefficient of the second molding layer is different from a thermal expansion coefficient of the first molding layer.Type: GrantFiled: October 17, 2019Date of Patent: January 14, 2025Assignee: NEPES CO., LTD.Inventors: Su Yun Kim, Dong Hoon Oh, Yong Tae Kwon, Jun Kyu Lee, Kyeong Rok Shin, Yong Woon Yeo
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Patent number: 12193252Abstract: A light emitting device includes: a first electrode and a second electrode with a surface facing the first electrode; an emission layer disposed between the first electrode and the second electrode and including a quantum dot (e.g., a plurality of quantum dots); and an electron auxiliary layer disposed between the emission layer and the second electrode. The electron auxiliary layer includes a first layer including a first metal oxide, and a second layer disposed on the first layer and including a second metal oxide. A roughness of an interface between the second layer and the second electrode is less than about 10 nm as determined by an electron microscopy analysis. An absolute value of a difference between a conduction band edge energy level of the second layer and a work function of the second electrode may be less than or equal to about 0.5 eV, and a conduction band edge energy level of the first layer may be less than the conduction band edge energy level of the second layer.Type: GrantFiled: April 14, 2023Date of Patent: January 7, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heejae Lee, Sung Woo Kim, Eun Joo Jang, Dae Young Chung, Moon Gyu Han
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Patent number: 12193313Abstract: A method of flash-curing a respective layer in an electronic device stack is provided. The method includes providing a stack of layers including a substrate and one or more electronically-active layers disposed on a surface of the substrate. The method further includes applying, over the stack of layers, a thermally-curable layer of material that includes a polymer or polymerizable material. The method further includes performing a non-equilibrium thermal process that includes raising a temperature of the thermally-curable layer of material, including the polymer or polymerizable material, above a first temperature for a length of time sufficient to cure the thermally-curable layer of material while maintaining the stack of layers below a second temperature that is less than the first temperature. The stack of layers is robust to temperatures below the second temperature.Type: GrantFiled: August 19, 2020Date of Patent: January 7, 2025Assignee: Sinovia TechnologiesInventors: George Burkhard, Daniel Slotcavage
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Patent number: 12193250Abstract: A light-emitting element includes a positive electrode, a negative electrode, a quantum dot layer provided between the positive electrode and the negative electrode and including quantum dots, and a first electron transport layer provided in contact with the quantum dot layer between the quantum dot layer and the negative electrode and containing a compound having a composition of ZnMO, constituent elements M in the composition being an element of at least one of Co, Rh, and Ir.Type: GrantFiled: May 31, 2019Date of Patent: January 7, 2025Assignee: SHARP KABUSHIKI KAISHAInventor: Yoshihiro Ueta
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Patent number: 12180066Abstract: A sensor package and a method for producing a sensor package are disclosed. In an embodiment a method for producing a sensor package includes providing a carrier including electric conductors, fastening a dummy die or interposer to the carrier, providing an ASIC device including an integrated sensor element and fastening the ASIC device to the dummy die or interposer.Type: GrantFiled: April 12, 2021Date of Patent: December 31, 2024Assignee: Sciosense B.V.Inventors: Willem Frederik Adrianus Besling, Casper Van Der Avoort, Coenraad Cornelis Tak, Remco Henricus Wilhelmus Pijnenburg, Olaf Wunnicke, Hendrik Bouman
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Patent number: 12178068Abstract: A display device is provided. An embodiment of a display device includes a first substrate, a second substrate disposed on the first substrate, first and second partition walls disposed on the second substrate, the second partition wall being disposed outside the first partition wall, a first trench disposed inside the first partition wall and having a first width, a second trench disposed between the first and second partition walls and having a second width greater than the first width; an alignment key disposed to overlap the second trench; a first spacer disposed on the alignment key, and a sealing member disposed along an edge between the first substrate and the second substrate without overlapping the alignment key, wherein the first spacer partially overlaps the first partition wall, the second partition wall, and the sealing member.Type: GrantFiled: July 25, 2023Date of Patent: December 24, 2024Assignee: Samsung Display Co., Ltd.Inventors: Jea Heon Ahn, Jang Soo Kim, Jong Hoon Kim, Seong Yeon Lee, Si Wan Jeon, Seok Joon Hong
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Patent number: 12170207Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.Type: GrantFiled: August 10, 2023Date of Patent: December 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsien-Wei Chen, Der-Chyang Yeh, Li-Hsien Huang
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Patent number: 12170330Abstract: An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.Type: GrantFiled: April 22, 2021Date of Patent: December 17, 2024Assignee: Lawrence Livermore National Security, LLCInventors: Adam Conway, Sara Elizabeth Harrison, Rebecca Nikolic, Qinghui Shao, Lars Voss
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Patent number: 12170245Abstract: A method includes providing a semiconductor structure having a metal gate structure (MG), gate spacers disposed on sidewalls of the MG, and a source/drain (S/D) feature disposed adjacent to the gate spacers; forming a first metal layer over the S/D feature and between the gate spacers; recessing the first metal layer to form a trench; forming a dielectric layer on sidewalls of the trench; forming a second metal layer over the first metal layer in the trench, wherein sidewalls of the second metal layer are defined by the dielectric layer; and forming a contact feature over the MG to contact the MG.Type: GrantFiled: July 22, 2022Date of Patent: December 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
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Patent number: 12166082Abstract: A silicon carbide semiconductor power transistor and a method of manufacturing the same. The silicon carbide semiconductor power transistor of the disclosure includes a substrate made of silicon carbide (SiC), a drift layer disposed on the substrate, a gate layer formed on the drift layer, a plurality of first and second well pick-up regions disposed in the drift layer, a plurality of source electrodes, and a plurality of contacts. A plurality of V-grooves is formed in the drift layer. A first opening is formed in the gate layer at a bottom of each of the V-grooves, and a second opening is formed in the gate layer at a top of the drift layer between the V-grooves. The plurality of contacts is disposed inside the second opening to be in direct contact with the second well pick-up regions.Type: GrantFiled: April 6, 2022Date of Patent: December 10, 2024Assignee: LEAP Semiconductor Corp.Inventors: Wei-Fan Chen, Kuo-Chi Tsai
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Patent number: 12166083Abstract: A nitride semiconductor device includes a channel layer, a barrier layer made of AlxInyGa1-x-yN (x>0, x+y?1), an active region that has a layered structure including the channel layer and the barrier layer, an inactive region that is formed at the layered structure around the active region and that is a concave portion having a bottom portion that reaches the channel layer, a gate layer made of a nitride semiconductor selectively formed on the barrier layer in the active region, a gate electrode formed on the gate layer, a first insulating film that covers the gate electrode and that is in contact with the barrier layer in the active region, and a second insulating film that covers the first insulating film and that is in contact with the inactive region.Type: GrantFiled: April 10, 2023Date of Patent: December 10, 2024Assignee: ROHM CO., LTD.Inventor: Yosuke Hata
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Patent number: 12161004Abstract: Embodiments of an electroluminescent device are described. The electroluminescent device includes a substrate, a first electrode disposed on the substrate, a first transport layer disposed on the first electrode, an emission layer having luminescent nanostructures disposed on the first transport layer, a second transport layer having an organic layer, and a second electrode disposed on the second transport layer. A first portion of the organic layer is disposed on the emission layer and a second portion of the organic layer is disposed on the first transport layer.Type: GrantFiled: October 21, 2021Date of Patent: December 3, 2024Assignee: Shoei Chemical Inc.Inventors: Daekyoung Kim, Ruiqing Ma
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Patent number: 12144196Abstract: A display substrate includes: a base substrate; a first conducting layer; a first insulating layer, where the first insulating layer is provided with a first opening; a second conducting layer, connected to the first conducting layer through the first opening, and including a first portion and a second portion, where the first portion is located within the first opening, and the second portion is located outside the first opening and located on the side of the first insulating layer facing away from the base substrate; and an inorganic protective layer including at least a first inorganic protective layer portion located between the second portion and the first insulating layer; in a direction perpendicular to the base substrate, the thickness h1 of the first inorganic protective layer portion and the thickness h2 of the second portion satisfy the following relationship: h2=K*h1, wherein 12?K?18.Type: GrantFiled: October 22, 2021Date of Patent: November 12, 2024Assignees: Chongqing BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Jie Li, Wei Zhang, Zeliang Li, Zhendong Li, Fei Fang
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Patent number: 12144193Abstract: An embodiment of a display device comprises a base substrate; an anode electrode disposed on the base substrate; a cathode electrode facing the anode electrode; and an organic light emitting layer disposed between the anode electrode and the cathode electrode, wherein the anode electrode includes: a first anode electrode disposed between the base substrate and the organic light emitting layer, a second anode electrode disposed between the first anode electrode and the organic light emitting layer, and a third anode electrode disposed between the second anode electrode and the organic light emitting layer, wherein a width of the first anode electrode is equal to or greater than a width of the second anode electrode.Type: GrantFiled: December 20, 2021Date of Patent: November 12, 2024Assignee: Samsung Display Co., Ltd.Inventors: Jong Hee Park, Hyoung Sik Kim
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Patent number: 12144232Abstract: The present application provides a display panel and a display device. The display panel comprises a first curved region located between two second curved regions and corresponding to a corner area of a planar region. The display panel comprises a supporting layer and a panel main body, and the supporting layer comprises a first portion being bent and within the first curved region and a second portion being bent and within the second curved region; the panel main body is disposed on the first portion and the second portion and bent along with the first portion and the second portion. a shrinkage rate of the first portion is greater than a shrinkage rate of the second portion.Type: GrantFiled: August 6, 2021Date of Patent: November 12, 2024Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventor: Ping He
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Patent number: 12137551Abstract: Some embodiments include an integrated assembly having a semiconductor-containing structure with a body region vertically between an upper region and a lower region. The upper region includes a first source/drain region. The lower region is split into two legs which are both joined to the body region. One of the legs includes a second source/drain region and the other of the legs includes a body contact region. The first and second source/drain regions are of a first conductivity type, and the body contact region is of a second conductivity type which is opposite to the first conductivity type. An insulative material is adjacent to the body region. A conductive gate is adjacent to the insulative material. A transistor includes the semiconductor-containing structure, the conductive gate and the insulative material. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: September 22, 2022Date of Patent: November 5, 2024Assignee: Micron Technology, Inc.Inventor: Werner Juengling