Patents Examined by Daniel Whalen
  • Patent number: 10991876
    Abstract: Methods of forming magnetic tunnel junction (MTJ) memory cells used in a magneto-resistive random access memory (MRAM) array are provided. A pre-clean process is performed to remove a metal oxide layer that may form on the top surface of the bottom electrodes of MTJ memory cells during the time the bottom electrode can be exposed to air prior to depositing MTJ layers. The pre-clean processes may include a remote plasma process wherein the metal oxide reacts with hydrogen radicals generated in the remote plasma.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Tang Wu, Wu Meng Yu, Szu-Hua Wu, Chin-Szu Lee
  • Patent number: 10978499
    Abstract: A display apparatus includes a substrate; a pixel driving circuit on the substrate; and a display unit connected with the pixel driving circuit, wherein the pixel driving circuit includes a first thin film transistor and a second thin film transistor, wherein the first thin film transistor includes, a first gate electrode on the substrate, a first active layer spaced apart from the first gate electrode and overlapping at least a part of the first gate electrode, a first source electrode connected with the first active layer; and a first drain electrode spaced apart from the first source electrode and connected with the first active layer, and wherein the second thin film transistor includes, a second active layer on the substrate, and a second gate electrode spaced apart from the second active layer and partially overlapping at least a part of the second active layer, wherein the first gate electrode is disposed between the substrate and the first active layer, the second active layer is disposed between the
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: April 13, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jaeman Jang, SeHee Park, DaeHwan Kim, PilSang Yun
  • Patent number: 10971526
    Abstract: A pixel structure includes a scan line, a data line, a reference voltage line, a first transistor, a second transistor, a third transistor, a first pixel electrode and a second pixel electrode. The reference voltage line is separated from the data line and intersected with the scan line. A first electrode of the second transistor, a second electrode of the second transistor and a first electrode of the third transistor have straight line portions overlapped with a second semiconductor pattern of the second transistor and a third semiconductor pattern of the third transistor. Both ends of each of the straight line portions are located outside a normal projection region of a first semiconductor pattern of the first transistor, a normal projection region of the second semiconductor pattern of the second transistor and a normal projection region of the third semiconductor pattern of the third transistor.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: April 6, 2021
    Assignee: Au Optronics Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Ya-Ling Hsu, Chen-Hsien Liao
  • Patent number: 10971640
    Abstract: A method (200) for fabricating patterns on the surface of a layer of a device (100), the method comprising: providing at least one layer (130, 230); adding at least one alkali metal (235) comprising Cs and/or Rb; controlling the temperature (2300) of the at least one layer, thereby forming a plurality of self-assembled, regularly spaced, parallel lines of alkali compound embossings (1300, 1305) at the surface of the layer. The method further comprises forming cavities (236, 1300) by dissolving the alkali compound embossings. The method (200) is advantageous for nanopatterning of devices (100) without using templates and for the production of high efficiency optoelectronic thin-film devices (100).
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 6, 2021
    Assignee: FLISOM AG
    Inventors: Patrick Reinhard, Adrian Chirila
  • Patent number: 10964843
    Abstract: An patterned Si substrate-based LED epitaxial wafer and a preparation method therefor, the LED epitaxial wafer comprising: a patterned Si substrate (1) and an Al2O3 coating (2) growing on the patterned Si substrate (1); sequentially growing on the Al2O3 coating (2) are a nucleating layer (3), a first buffer layer (4), a first insertion layer (5), a second buffer layer (6), a second insertion layer (7), an n-GaN layer (8), a quantum well layer (9), a p-GaN layer (10), an n-electrode (14) electrically connected to the n-GaN layer and a p-electrode (13) electrically connected to the p-GaN layer. The present invention is suitable for the preparation of large-sized LED epitaxial wafers. Furthermore, the crystal quality is improved, and the light extraction efficiency of the LED die is improved.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: March 30, 2021
    Assignee: ENKRIS SEMICONDUCTOR, INC
    Inventors: Liyang Zhang, Kai Cheng
  • Patent number: 10964771
    Abstract: A display panel including a substrate including a display area surrounding an opening area and a non-display area between the opening area and the display area; a plurality of display elements on the display area; a plurality of scan lines extending in a first direction and detouring around an edge of the opening area; a plurality of data lines extending in a second direction that intersects with the first direction, the plurality of data lines detouring around the edge of the opening area; and a plurality of emission control lines extending in the first direction and detouring around the edge of the opening area.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Minku Lee, Jihyun Ka, Kwangsae Lee
  • Patent number: 10948447
    Abstract: An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: March 16, 2021
    Assignee: Regents of the University of Minnesota
    Inventor: Steven J. Koester
  • Patent number: 10950652
    Abstract: Disclosed herein is a light-emitting device.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: March 16, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Chien-Fu Shen, Chao-Hsing Chen, Tsun-Kai Ko, Schang-Jing Hon, Sheng-Jie Hsu, De-Shan Kuo, Hsin-Ying Wang, Chiu-Lin Yao, Chien-Fu Huang, Hsin-Mao Liu, Chien-Kai Chung
  • Patent number: 10943990
    Abstract: Gate contact over active layout designs are provided. In one aspect, a method for forming a gate contact over active device includes: forming a device including metal gates over an active area of a wafer, and source/drains on opposite sides of the metal gates offset by gate spacers; recessing the metal gates/gate spacers; forming etch-selective spacers on top of the recessed gate spacers; forming gate caps on top of the recessed metal gates; forming source/drain contacts on the source/drains; forming source/drain caps on top of the source/drain contacts, wherein the etch-selective spacers provide etch selectivity to the gate caps and source/drain caps; and forming a metal gate contact that extends through one of the gate caps, wherein the etch-selective spacers prevent gate-to-source drain shorting by the metal gate contact. Alternate etch-selective configurations are also provided including a claw-shaped source/drain cap design. A gate contact over active device is also provided.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Andrew Greene, Victor W. C. Chan, Gangadhara Raja Muthinti, Veeraraghavan Basker, Junli Wang, Kisik Choi, Su Chen Fan
  • Patent number: 10943839
    Abstract: An apparatus, system and method are disclosed for a manufactured imager system. The apparatus, system and method may include an imager comprising a plurality of photosites divisible into a plurality of subsections, and at least one wafer-level lens additively composed of a plurality of material layers successively deposited directly upon the imager to achieve a predetermined optical performance for each of the plurality of subsections. The material layers may comprise one or more of a photopolymer, a thermoplastic resin, a low temperature melting glass, and a glass sheet, and may be uniform or non-uniform.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: March 9, 2021
    Assignee: JABIL INC.
    Inventor: Girish S. Wable
  • Patent number: 10937507
    Abstract: A bit line driver device includes a semiconductor substrate and at least one isolation structure disposed in the semiconductor substrate. Active regions are defined in the semiconductor substrate by the at least one isolation structure. Each of the active regions is elongated in a first direction, and two of the active regions are disposed adjacent to each other in a second direction. Each of the active regions includes a first portion, a second portion, and a third portion. The third portion is disposed between the first portion and the second portion in the first direction. A width of the third portion is smaller than a width of the first portion and a width of the second portion. The distance between the two adjacent active regions may be increased by the third portions accordingly.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: March 2, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Liang Chen
  • Patent number: 10937909
    Abstract: Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (FinFETs), and disclosed are the associated devices. An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer. The fin portion of the substrate, the first semiconductor material layer, the first semiconductor oxide layer, and the second semiconductor material layer form a fin. The method further includes forming a gate stack overwrapping the fin.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Gwan-Sin Chang, Kuo-Cheng Ching, Zhiqiang Wu
  • Patent number: 10923514
    Abstract: In various embodiments, etchants featuring (i) mixtures of hydrochloric acid, methanesulfonic acid, and nitric acid, or (ii) mixtures of phosphoric acid, methanesulfonic acid, and nitric acid, are utilized to etch metallic bilayers while minimizing resulting etch discontinuities between the layers of the bilayer.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: February 16, 2021
    Assignees: H.C. STARCK INC., DAETEC. LLC
    Inventors: Patrick Hogan, John Moore, Alex Brewer, Jared Pettit
  • Patent number: 10910373
    Abstract: Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gun You, Se-wan Park, Baik-Min Sung, Bo-Cheol Jeong
  • Patent number: 10903559
    Abstract: A method for manufacturing a liquid-crystal antenna device is provided. The method includes step (a) providing a first mother substrate. The first mother substrate includes a first region and a second region. The first region has a plurality of first sides. An extension line of at least one of the first sides divides the second region into a first part and a second part. The method also includes the following steps: (b) forming a first electrode layer on the first region and the second region, and (c) cutting the first mother substrate along the first sides of the first region.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: January 26, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Yi-Hung Lin, Chin-Lung Ting, Hui-Min Huang, Tang-Chin Hung
  • Patent number: 10892432
    Abstract: An organic EL display device includes a blue pixel, and a second pixel configured to output light having a peak wavelength longer than that of blue light. The blue pixel includes a blue phosphorescent luminescent material containing layer and a blue fluorescent luminescent material containing layer as common layers common to the plurality of pixels, and the second pixel includes a second phosphorescent luminescent material containing layer provided in each of the second pixel, adjacently to the common layers at the side of an anode from the common layers.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: January 12, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Manabu Niboshi, Shinichi Kawato, Tokiyoshi Umeda, Yuto Tsukamoto, Hiroshi Imada
  • Patent number: 10892331
    Abstract: Techniques are provided to fabricate semiconductor integrated circuit devices which include complementary metal-oxide-semiconductor gate-all-around field-effect transistor devices (e.g., nanosheet field-effect transistor devices), wherein the channel orientation layout of N-type and P-type field-effect transistor devices are independently configured to provide enhanced carrier mobility in the channel layers of the different type field-effect transistor devices.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Tenko Yamashita, Myung-Hee Na
  • Patent number: 10892405
    Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: January 12, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
  • Patent number: 10886162
    Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 5, 2021
    Assignee: Soitec
    Inventors: Arnaud Castex, Oleg Kononchuk
  • Patent number: 10886492
    Abstract: An array substrate and a manufacturing method thereof, and a display panel are disclosed. The array substrate includes a base substrate, comprising a plurality of sub-pixel regions and inter-sub-pixel regions between adjacent sub-pixel regions; and a first organic functional layer on the base substrate. At least a portion of the first organic functional layer is in the plurality of sub-pixel regions; and the first organic functional layer includes at least one fracture opening, the at least one fracture opening is configured to block a transportation of the carriers between adjacent sub-pixel regions.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: January 5, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaohu Li, Zhiqiang Jiao, Tun Liu, Huajie Yan, Hongsheng Zhan, Liangliang Kang