Abstract: A fin-like field-effect transistor (FinFET) device is disclosed. The device includes a semiconductor substrate having a source/drain region, a plurality of isolation regions over the semiconductor substrate and a source/drain feature in the source/drain region. The source/drain feature includes a multiple plug-type portions over the substrate and each of plug-type portion is isolated each other by a respective isolation region. The source/drain feature also includes a single upper portion over the isolation regions. Here the single upper portion is merged from the multiple plug-type portions. The single upper portion has a flat top surface facing away from a top surface of the isolation region.

Abstract: A light emitting element includes a first electrode, an organic layer formed on the first electrode and including a luminescent layer composed of an organic luminescent material and a second electrode formed on the organic layer, and further includes a light reflecting layer provided below the first electrode. Light emitted in the luminescent layer is resonated between the light reflecting layer and an interface of the second electrode and the organic layer, and a portion of the light is output from the second electrode.

Abstract: The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes: a substrate; and a light-emitting device and a packaging structure on the substrate, the packaging structure sealing the light-emitting device on the substrate. The light-emitting device includes a cathode, an anode, and a light-emitting layer between the cathode and the anode; the packaging structure includes a first inorganic packaging layer, and the first inorganic packaging layer includes a first inorganic packaging sublayer, a second inorganic packaging sublayer, and a third inorganic packaging sublayer that are sequentially stacked; and a refractive index of the second inorganic packaging sublayer is greater than a refractive index of the first inorganic packaging sublayer, and a difference between the refractive index of the second inorganic packaging sublayer and the refractive index of the first inorganic packaging sublayer is greater than 0.

Abstract: Disclosed is a display device which may display images in a transmission portion, and may improve uniformity of a display in both the emission portion and the transmission portion, thus may improve efficiency of a device and improve a lifespan.

Abstract: A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; agate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions.

Abstract: A light emitting diode of an embodiment of the present disclosure includes a first electrode, a hole transport region on an upper portion of the first electrode and having a first refractive index, an emission layer on an upper portion of the hole transport region and having a second refractive index less than the first refractive index, an electron transport region on an upper portion of the emission layer, and a second electrode on an upper portion of the electron transport region.

Abstract: There is provided a solid-state imaging device including: one or more photoelectric conversion elements provided on side of a first surface of a semiconductor substrate; a through electrode coupled to the one or more photoelectric conversion elements, and provided between the first surface and a second surface of the semiconductor substrate; and an amplifier transistor and a floating diffusion provided on the second surface of the semiconductor substrate, in which the one or more photoelectric conversion elements are coupled to a gate of the amplifier transistor and the floating diffusion via the through electrode.

Abstract: A light emitting device includes a substrate; a first electrode disposed on the substrate; an organic material layer disposed on the first electrode and including a first resonance auxiliary layer; and a second electrode disposed on the organic material layer, wherein the first resonance auxiliary layer includes a first compound with a lowest unoccupied molecular orbital (LUMO) level of ?4 eV or less and a second compound with a highest occupied molecular orbital (HOMO) level of ?4 eV or less, and wherein the first resonance auxiliary layer has a thickness of 20% to 90% of a total thickness of the organic material layer.

Abstract: An organic electroluminescence device includes a first emitting unit, a first charge generating layer, a second emitting unit, a second charge generating layer, and a third emitting unit provided between an anode and a cathode in this order from the anode, in which the second charge generating layer includes an N layer close to the anode and a P layer close to the cathode, the third emitting layer contains a blue fluorescent compound, at least one of the first or second emitting layer contains a blue fluorescent compound, the third emitting unit includes a hole transporting zone between the second charge generating layer and the third emitting layer, the hole transporting zone is in contact with the second charge generating layer, and a thickness of the hole transporting zone is in a range from 5 nm to 40 nm and smaller than a thickness of the N layer.

Abstract: A display module includes a substrate; light emitting diodes, first connection pads, second connection pads, and side wirings. The light emitting diodes are arranged on one surface of the substrate. The first connection pads are formed on the one surface of the substrate. The second connection pads are formed on an opposite surface of the one surface. The side wirings are formed on each of a first edge of the substrate and a second edge of the substrate that is adjacent to the first edge. The side wirings electrically couple the first connection pads on the one surface of the substrate with respective ones of the second connection pads on the opposite surface.

Abstract: Methods of forming magnetic tunnel junction (MTJ) memory cells used in a magneto-resistive random access memory (MRAM) array are provided. A pre-clean process is performed to remove a metal oxide layer that may form on the top surface of the bottom electrodes of MTJ memory cells during the time the bottom electrode can be exposed to air prior to depositing MTJ layers. The pre-clean processes may include a remote plasma process wherein the metal oxide reacts with hydrogen radicals generated in the remote plasma.

Abstract: An OLED lighting device comprising: a blue light-emitting unit with a blue-light fluorescent, phosphorescent or TADF emitter; a yellow light-emitting electroluminescent unit comprising a green phosphorescent emitter, a red phosphorescent emitter and at least one non-emitting host; wherein the blue light-emitting unit and the yellow light-emitting unit are separated by a mixed interlayer with two non-emitting charge-carrier materials. Desirably, the yellow-light emitting unit essentially consists of a green phosphorescent emitter, a red phosphorescent emitter and a single non-emitting host. The mixed interlayer desirably has more than 50% of a hole-transporting material and an electron-transporting material. The Triplet Energy of both materials in the mixed interlayer can be higher than the Triplet Energies of the R and G phosphorescent dopants.

Abstract: A display device includes a first pixel area including a first pixel electrode and a first organic light emitting layer, a tandem pixel area including a tandem pixel electrode, a first tandem organic light emitting layer and a second tandem organic light emitting layer, a capping layer including a first capping layer corresponding to the first organic light emitting layer and a tandem capping layer corresponding to both the first tandem organic light emitting layer and the second tandem organic light emitting layer, and a common electrode between the first capping layer and the first organic light emitting layer and between the tandem capping layer and the second tandem organic light emitting layer. Each of the first capping layer and the tandem capping layer has a thickness, and the thickness of the tandem capping layer is smaller than the thickness of the first capping layer.

Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

Abstract: A color conversation panel according to an embodiment may include partitioning walls disposed on a substrate, reflective layers disposed on outer surfaces of the partitioning walls, overcoats disposed outside on outer surfaces of the reflective layers and having water repellency, a spacer overlapping a part of the partitioning walls and protruding from a part of the overcoats, the spacer and the overcoats being formed on a same layer, and color conversion layers disposed on the overcoats and disposed in areas defined by the partitioning walls.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC has a plurality of logic devices disposed on a logic region of a substrate, including a first logic device configured to operate at a first voltage and comprising a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along sidewall and bottom surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed conformally along the first logic gate dielectric within the logic device trench. A hard mask layer is disposed on the first logic gate electrode within the logic device trench.