Abstract: An organic light emitting diode and a manufacturing method thereof, a display panel are provided. The organic light emitting diode includes a light emitting structure and a first electrode structure. The first electrode structure is configured to drive the light emitting structure to emit light and includes a first electrode and a light reflecting layer, the light reflecting layer is disposed on a side of the first electrode away from the light emitting structure, wherein the first electrode and at least a portion of the light reflecting layer are overlapped with each other in a first direction, an insulating layer is at least partially disposed between the at least part of the light reflecting layer and the first electrode overlapped with each other, and the first direction is perpendicular to a plane on which the light reflecting layer is located.

Abstract: A mask assembly and an organic light emitting display device manufactured using the mask assembly are capable of realizing an organic light emitting display device having a hole in a display area, the mask assembly including a frame defining a first opening area, a first mask on the frame and defining a plurality of second opening areas that overlap the first opening area, and a second mask fixed to the frame across the plurality of second opening areas, and including a body portion overlapping the first mask, a blocking portion at each respective one of the second opening areas, and a pattern portion between the body portion and the blocking portion, and defining a plurality of holes.

Abstract: A stacked three dimensional semiconductor device includes multiple thin substrates stacked over one another and over a base substrate. The thin substrates may include a thickness of about 0.1 ?m. In some embodiments, a noise suppression tier is vertically interposed between active device tiers. In some embodiments, each tier includes active device portions and noise suppression portions and the tiers are arranged such that noise suppression portions are vertically interposed between active device portions. The noise suppression portions include decoupling capacitors in a power/ground mesh and alleviate vertical noise.

Abstract: Embodiments of the present disclosure provide a display panel and an electronic device. The display panel includes: a back plate; a light emitting element on a side of the back plate; a circular polarizer on a side of the light emitting element away from the back plate; a wave plate on a side of the polarizer away from the back plate; and an anti-glare film layer on a side of the wave plate away from the back plate.

Abstract: A method for manufacturing a transistor being a bottom-gate transistor is provided. The method for manufacturing a transistor includes a step of forming a first metal layer 32 on an insulator layer 20 provided on a substrate 10 including a gate electrode, a step of applying a resist onto the first metal layer 32, and patterning the first metal layer 32 by a photolithographic method, an oxide film removal step of removing an oxide film 26 formed on the patterned first metal layer 32, and a step of forming a source electrode and a drain electrode by forming a second metal layer 42 on the first metal layer 32.

Abstract: Plural sessions of proton irradiation are performed by differing ranges from a substrate rear surface side. After first to fourth n-type layers of differing depths are formed, the protons are activated. Next, helium is irradiated to a position deeper than the ranges of the proton irradiation from the substrate rear surface, introducing lattice defects. When the amount of lattice defects is adjusted by heat treatment, protons not activated in a fourth n-type layer are diffused, forming a fifth n-type layer contacting an anode side of the fourth n-type layer and having a carrier concentration distribution that decreases toward the anode side by a more gradual slope than that of the fourth n-type layer. The fifth n-type layer that includes protons and helium and the first to fourth n-type layers that include protons constitute an n-type FS layer. Thus, a semiconductor device having improved reliability and lower cost may be provided.

Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

Abstract: A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; a gate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions.

Abstract: A packaged micro-electro-mechanical system (MEMS) device (100) comprises a circuitry chip (101) attached to the pad (110) of a substrate with leads (111), and a MEMS (150) vertically attached to the chip surface by a layer (140) of low modulus silicone compound. On the chip surface, the MEMS device is surrounded by a polyimide ring (130) with a surface phobic to silicone compounds. A dome-shaped glob (160) of cured low modulus silicone material covers the MEMS and the MEMS terminal bonding wire spans (180); the glob is restricted to the chip surface area inside the polyimide ring and has a surface non-adhesive to epoxy-based molding compounds. A package (190) of polymeric molding compound encapsulates the vertical assembly of the glob embedding the MEMS, the circuitry chip, and portions of the substrate; the molding compound is non-adhering to the glob surface yet adhering to all other surfaces.

Abstract: Alight-emitting element includes an anode electrode, a cathode electrode, a light-emitting layer, a positive hole transport layer, and an electron transport layer. The light-emitting layer, the positive hole transport layer, and the electron transport layer are provided between the anode electrode and the cathode electrode. The light-emitting layer includes QD phosphor particles, a positive hole transport substance configured to transport positive holes transported thereto by the positive hole transport layer, an electron transport substance configured to transport electrons transported thereto by the electron transport layer, and a photosensitive host material.

Abstract: A light emitting diode of an embodiment of the present disclosure includes a first electrode, a hole transport region on an upper portion of the first electrode and having a first refractive index, an emission layer on an upper portion of the hole transport region and having a second refractive index less than the first refractive index, an electron transport region on an upper portion of the emission layer, and a second electrode on an upper portion of the electron transport region.

Abstract: A semiconductor package includes an outer redistributed line (RDL) structure, a first semiconductor chip disposed on the outer RDL structure, a stack module stacked on the first semiconductor chip, and a bridge die stacked on the outer RDL structure. A portion of the stack module laterally protrudes from a side surface of the first semiconductor chip. The bridge die supports the protruding portion of the stack module. The stack module includes an inner RDL structure, a second semiconductor chip disposed on the inner RDL structure, a capacitor die disposed on the inner RDL structure, and an inner encapsulant. The capacitor die acts as a decoupling capacitor of the second semiconductor chip.

Abstract: Some embodiments include an integrated assembly having a semiconductor-containing structure with a body region vertically between an upper region and a lower region. The upper region includes a first source/drain region. The lower region is split into two legs which are both joined to the body region. One of the legs includes a second source/drain region and the other of the legs includes a body contact region. The first and second source/drain regions are of a first conductivity type, and the body contact region is of a second conductivity type which is opposite to the first conductivity type. An insulative material is adjacent to the body region. A conductive gate is adjacent to the insulative material. A transistor includes the semiconductor-containing structure, the conductive gate and the insulative material. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.

Abstract: A field effect transistor, comprising a gate contact and gate metal forming a vertical structure, such vertical structure having sides and a top surrounded by an air gap formed between a source electrode and a drain electrode of the field effect transistor.

Abstract: Provided is an optical device including an active layer, which includes two outer barriers and a coupled quantum well between the two outer barriers. The coupled quantum well includes a first quantum well layer, a second quantum well layer, a third quantum well layer, a first coupling barrier between the first quantum well layer and the second quantum well layer, and a second coupling barrier between the second quantum well layer and the third quantum well layer. The second quantum well layer is between the first quantum well layer and the third quantum well layer. An energy band gap of the second quantum well layer is less than an energy band gap of the first quantum well layer, and an energy band gap of the third quantum well layer is equal to or less than the energy band gap of the second quantum well layer.

Abstract: A light-emitting device with light emission efficiency and a display apparatus are provided. The light-emitting device includes a first organic light emission material layer generating light of a first wavelength, a second organic light emission material layer generating light of a second wavelength different from the first wavelength, and a third organic light emission material layer generating light of a third wavelength different from the first and second wavelengths, the first organic light emission material layer may be located at a position comprising a first antinode having a resonance wavelength resonating in a micro cavity, and the second organic light emission material layer and the third organic light emission material layer may be located at a position comprising a second antinode having the resonance wavelength resonating in the micro cavity.

Abstract: A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

Abstract: A display panel including a substrate, anodes disposed on or above the substrate, light-emitting layers disposed on or above the anodes, a first intermediate layer disposed on or above the light-emitting layers, a second intermediate layer disposed on the first intermediate layer, and a cathode disposed on or above the second intermediate layer. The first intermediate layer includes a fluoride of a first metal or a complex of the first metal. The second intermediate layer includes a second metal. The anodes are light-transmissive and the cathode is light-reflective, or the anodes are light-reflective and the cathode is light-transmissive. The first metal is selected from a group consisting of alkali metals and alkaline earth metals. The second metal is selected from rare earth metals.

Abstract: A light emitting structure comprises a substrate, a plurality of sub-pixel stacks over the substrate emitting different colors, a bank surrounding the sub-pixel stacks and forming an interior space above the sub-pixel stacks, a first filler material in the interior space, a second filler material over the first filler material, and an interface between the first filler material and the second filler material. Each of the sub-pixel stacks including an emissive layer between a first transport layer and a second transport layer, a first electrode layer coupled to the first transport layer, and a second electrode layer coupled to the second transport layer. The sub-pixel stacks each have a substantially uniform distance between the emissive layer and the first electrode layer. Each of the sub-pixel stacks emits a main emission peak at one direction normal to a top surface of each of the sub-pixel stacks through the interface.