Abstract: A display apparatus includes a substrate; a pixel driving circuit on the substrate; and a display unit connected with the pixel driving circuit, wherein the pixel driving circuit includes a first thin film transistor and a second thin film transistor, wherein the first thin film transistor includes, a first gate electrode on the substrate, a first active layer spaced apart from the first gate electrode and overlapping at least a part of the first gate electrode, a first source electrode connected with the first active layer; and a first drain electrode spaced apart from the first source electrode and connected with the first active layer, and wherein the second thin film transistor includes, a second active layer on the substrate, and a second gate electrode spaced apart from the second active layer and partially overlapping at least a part of the second active layer, wherein the first gate electrode is disposed between the substrate and the first active layer, the second active layer is disposed between the

Abstract: A nitride semiconductor device includes a channel layer, a barrier layer made of AlxInyGa1-x-yN (x>0, x+y?1), an active region that has a layered structure including the channel layer and the barrier layer, an inactive region that is formed at the layered structure around the active region and that is a concave portion having a bottom portion that reaches the channel layer, a gate layer made of a nitride semiconductor selectively formed on the barrier layer in the active region, a gate electrode formed on the gate layer, a first insulating film that covers the gate electrode and that is in contact with the barrier layer in the active region, and a second insulating film that covers the first insulating film and that is in contact with the inactive region.

Abstract: A method for manufacturing a liquid-crystal antenna device is provided. The method includes step (a) providing a first mother substrate. The first mother substrate includes a first region and a second region. The first region has a plurality of first sides. An extension line of at least one of the first sides divides the second region into a first part and a second part. The method also includes the following steps: (b) forming a first electrode layer on the first region and the second region, and (c) cutting the first mother substrate along the first sides of the first region.

Abstract: Embodiments of a display device are described. A display device includes first and second sub-pixels. The first sub-pixel includes a first light source having a quantum dot (QD) film, a blocking layer disposed on the QD film, and a first portion of an organic phosphor film disposed on the blocking layer and a first substrate configured to support the first light source. The blocking layer is configured to prevent emission of light from the first portion of the organic phosphor film and the QD film is configured to emit a primary emission peak wavelength in a red, green, cyan, yellow, or magenta wavelength region of an electromagnetic (EM) spectrum. The second sub-pixel includes a second light source and a second substrate configured to support the second light source. The second light source has a second portion of the organic phosphor film disposed adjacent to the QD film.

Abstract: An electroluminescent display panel and a manufacturing method thereof, and a display device. Each of a plurality of pixel units included in the electroluminescent display panel includes a first sub-pixel, a second sub-pixel and a third sub-pixel, respectively, each of the sub-pixels includes a first electrode, and a light-emitting layer, respectively, taking a planar surface of the first electrode facing the light-emitting layer as a reference plane, the light-emitting layer of the first sub-pixel is on a first anti-node of a first standing wave, the light-emitting layer of the second sub-pixel is on a second anti-node of a second standing wave, and the light-emitting layer of the third sub-pixel is on a second anti-node of a third standing wave.

Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.

Abstract: A semiconductor structure includes a metal gate structure (MG) disposed over a semiconductor substrate, gate spacers disposed on sidewalls of the MG, and a gate contact disposed on the MG. The semiconductor structure further includes an etch-stop layer (ESL) disposed on the gate spacers, and a source/drain (S/D) contact disposed adjacent to the gate spacers, where a top portion of the S/D contact defined by the ESL is narrower than a bottom portion of the S/D contact defined by the gate spacers.

Abstract: Provided is a display device. The display device includes a first substrate and a second substrate which are formed of different materials; a first LED disposed on the first substrate; and a second LED and a third LED disposed on the second substrate, in which the first LED, the second LED, and the third LED are disposed between the first substrate and the second substrate. Therefore, in consideration of the growth efficiency of the LEDs which emit different colored light, the first LED is disposed on the first substrate and the second LED and the third LED are disposed on the second substrate which is formed of a different material from the first substrate, thereby improving the growth efficiency of the plurality of LEDs.

Abstract: A substrate is described with a thermal dissipation structure sintered to thermal vias. In one example, a microelectronic module includes a recess between first and second substrate surfaces. One or more thermal vias extend between the first substrate surface and the interior recess surface, wherein each of the thermal vias has an interior end exposed at the interior recess surface. A sintered metal layer is in the recess and in physical contact with the interior end of the thermal vias and a thermal dissipation structure is in the recess over the sintered metal layer. The thermal dissipation structure is attached to the substrate within the recess by the sintered metal layer, and the thermal dissipation structure is thermally coupled to the thermal vias through the sintered metal layer.

Abstract: A pixel unit, comprising a plurality of sub-pixels of different colors, wherein each of the sub-pixels comprises a first electrode layer, a second electrode layer, and a light-emitting layer disposed between the first electrode layer and the second electrode layer; and in the plurality of sub-pixels of the different colors, an interference intensity of light emitted by the light-emitting layer of the sub-pixel of a target color is greater than an interference intensity of light emitted by the light-emitting layers of the sub-pixels of other colors; wherein the interference intensity means an interference intensity between reflected light produced when light emitted by the light-emitting layer of the sub-pixel is frequently reflected between the layers of the sub-pixel.

Abstract: An organic light-emitting display (OLED) panel includes a substrate and a light-emitting pixel array disposed on the substrate and including a plurality of light-emitting pixels, each of the plurality of light-emitting pixels includes a concave structure, a light-emitting layer, a planarization layer, and a convex microlens which are sequentially stacked up and aligned up on the substrate in such a manner that light emitted in an angle perpendicular to the light-emitting layer on the concave structure pass through an focal point of the convex microlens.

Abstract: A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place.

Abstract: An optical semiconductor element includes a single crystal AlN substrate; an n-type semiconductor layer having an AlGaN layer, the AlGaN layer being grown on the AlN substrate and being pseudomorphic with the AlN substrate, an Al composition of the AlGaN layer being reduced with an increase in distance from the AlN substrate; an active layer grown on the n-type semiconductor layer and having a multiple quantum well structure which includes a plurality of well layers and barrier layers; and a p-type semiconductor layer which is grown on the active layer. The single crystal AlN substrate has a dislocation density being 106 cm?2 or less.

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

Abstract: An electroluminescent device and a display device including the same. The electroluminescent device includes a first electrode and a second electrode facing each other; a light emitting layer disposed between the first electrode and the second electrode, the light emitting layer including a quantum dot; a hole transport layer disposed between the light emitting layer and the first electrode; and an electron transport layer disposed between the light emitting layer and the second electrode, wherein the hole transport layer, the light emitting layer, or a combination thereof includes thermally activated delayed fluorescence material, and the thermally activated delayed fluorescence material is present in an amount of greater than or equal to about 0.01 wt % and less than about 10 weight percent (wt %), based on 100 wt % of the hole transport layer, the light emitting layer, or the combination thereof including the thermally activated delayed fluorescence material.

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and distal regions proximate the control gate regions. The control gate regions have front surfaces, top surfaces and bottom surfaces. The top and bottoms surfaces extend back from the front surfaces. High-k dielectric material is along the control gate regions. The high-k dielectric material has first regions along the top and bottom surfaces, and has second regions along the front surfaces. The first regions are thicker than the second regions. Charge-blocking material is adjacent to the second regions of the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. Gate-dielectric material is adjacent to the charge-storage material. Channel material is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies.

Abstract: An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.

Abstract: A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.

Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

Abstract: A chip-scale sensor package structure includes a sensor chip, a first package body surrounding and connected to an outer lateral side of the sensor chip, a ring-shaped support disposed on a top side of the first package body, a light permeable member disposed on the ring-shaped support, and a redistribution layer (RDL) disposed on a bottom surface of the sensor chip and a bottom side of the first package body. The sensor chip includes a sensing region arranged on the top surface thereof, a plurality of internal contacts, and a plurality of conductive paths respectively connected to the internal contacts and electrically coupled to the sensing region. The sensing region is spaced apart from the ring-shaped support by a distance less than 300 ?m. A bottom surface of the RDL has a plurality of external contacts electrically coupled to the internal contacts.