Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

Abstract: A method and a semiconductor device includes a substrate, and a first device type formed on the substrate, the first device type including an active channel region including a first fin, the first fin including a first fin width which is narrower than a second fin width above and below the active channel region. A second device type can be formed on the same substrate, the second device type includes a second active channel region including a second fin, the second fin including a first fin width which is the same as the second fin width both above and below the second active channel region.

Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

Abstract: An optical semiconductor element comprises: an AlN substrate; an n-type semiconductor layer composed of an AlGaN layer, the AlGaN layer being grown on the AlN substrate and being pseudomorphic with the AlN substrate, an Al composition or the AlGaN layer being reduced with an increase in distance from the AlN substrate; an active layer which is grown on the n-type semiconductor layer; and a p-type semiconductor layer which is grown on the active layer.

Abstract: Methods of forming magnetic tunnel junction (MTJ) memory cells used in a magneto-resistive random access memory (MRAM) array are provided. A pre-clean process is performed to remove a metal oxide layer that may form on the top surface of the bottom electrodes of MTJ memory cells during the time the bottom electrode can be exposed to air prior to depositing MTJ layers. The pre-clean processes may include a remote plasma process wherein the metal oxide reacts with hydrogen radicals generated in the remote plasma.

Abstract: A display apparatus includes a substrate; a pixel driving circuit on the substrate; and a display unit connected with the pixel driving circuit, wherein the pixel driving circuit includes a first thin film transistor and a second thin film transistor, wherein the first thin film transistor includes, a first gate electrode on the substrate, a first active layer spaced apart from the first gate electrode and overlapping at least a part of the first gate electrode, a first source electrode connected with the first active layer; and a first drain electrode spaced apart from the first source electrode and connected with the first active layer, and wherein the second thin film transistor includes, a second active layer on the substrate, and a second gate electrode spaced apart from the second active layer and partially overlapping at least a part of the second active layer, wherein the first gate electrode is disposed between the substrate and the first active layer, the second active layer is disposed between the

Abstract: A method (200) for fabricating patterns on the surface of a layer of a device (100), the method comprising: providing at least one layer (130, 230); adding at least one alkali metal (235) comprising Cs and/or Rb; controlling the temperature (2300) of the at least one layer, thereby forming a plurality of self-assembled, regularly spaced, parallel lines of alkali compound embossings (1300, 1305) at the surface of the layer. The method further comprises forming cavities (236, 1300) by dissolving the alkali compound embossings. The method (200) is advantageous for nanopatterning of devices (100) without using templates and for the production of high efficiency optoelectronic thin-film devices (100).

Abstract: A pixel structure includes a scan line, a data line, a reference voltage line, a first transistor, a second transistor, a third transistor, a first pixel electrode and a second pixel electrode. The reference voltage line is separated from the data line and intersected with the scan line. A first electrode of the second transistor, a second electrode of the second transistor and a first electrode of the third transistor have straight line portions overlapped with a second semiconductor pattern of the second transistor and a third semiconductor pattern of the third transistor. Both ends of each of the straight line portions are located outside a normal projection region of a first semiconductor pattern of the first transistor, a normal projection region of the second semiconductor pattern of the second transistor and a normal projection region of the third semiconductor pattern of the third transistor.

Abstract: A display panel including a substrate including a display area surrounding an opening area and a non-display area between the opening area and the display area; a plurality of display elements on the display area; a plurality of scan lines extending in a first direction and detouring around an edge of the opening area; a plurality of data lines extending in a second direction that intersects with the first direction, the plurality of data lines detouring around the edge of the opening area; and a plurality of emission control lines extending in the first direction and detouring around the edge of the opening area.

Abstract: An patterned Si substrate-based LED epitaxial wafer and a preparation method therefor, the LED epitaxial wafer comprising: a patterned Si substrate (1) and an Al2O3 coating (2) growing on the patterned Si substrate (1); sequentially growing on the Al2O3 coating (2) are a nucleating layer (3), a first buffer layer (4), a first insertion layer (5), a second buffer layer (6), a second insertion layer (7), an n-GaN layer (8), a quantum well layer (9), a p-GaN layer (10), an n-electrode (14) electrically connected to the n-GaN layer and a p-electrode (13) electrically connected to the p-GaN layer. The present invention is suitable for the preparation of large-sized LED epitaxial wafers. Furthermore, the crystal quality is improved, and the light extraction efficiency of the LED die is improved.

Abstract: Disclosed herein is a light-emitting device.

Abstract: An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.

Abstract: An apparatus, system and method are disclosed for a manufactured imager system. The apparatus, system and method may include an imager comprising a plurality of photosites divisible into a plurality of subsections, and at least one wafer-level lens additively composed of a plurality of material layers successively deposited directly upon the imager to achieve a predetermined optical performance for each of the plurality of subsections. The material layers may comprise one or more of a photopolymer, a thermoplastic resin, a low temperature melting glass, and a glass sheet, and may be uniform or non-uniform.

Abstract: Gate contact over active layout designs are provided. In one aspect, a method for forming a gate contact over active device includes: forming a device including metal gates over an active area of a wafer, and source/drains on opposite sides of the metal gates offset by gate spacers; recessing the metal gates/gate spacers; forming etch-selective spacers on top of the recessed gate spacers; forming gate caps on top of the recessed metal gates; forming source/drain contacts on the source/drains; forming source/drain caps on top of the source/drain contacts, wherein the etch-selective spacers provide etch selectivity to the gate caps and source/drain caps; and forming a metal gate contact that extends through one of the gate caps, wherein the etch-selective spacers prevent gate-to-source drain shorting by the metal gate contact. Alternate etch-selective configurations are also provided including a claw-shaped source/drain cap design. A gate contact over active device is also provided.

Abstract: Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (FinFETs), and disclosed are the associated devices. An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer. The fin portion of the substrate, the first semiconductor material layer, the first semiconductor oxide layer, and the second semiconductor material layer form a fin. The method further includes forming a gate stack overwrapping the fin.

Abstract: A bit line driver device includes a semiconductor substrate and at least one isolation structure disposed in the semiconductor substrate. Active regions are defined in the semiconductor substrate by the at least one isolation structure. Each of the active regions is elongated in a first direction, and two of the active regions are disposed adjacent to each other in a second direction. Each of the active regions includes a first portion, a second portion, and a third portion. The third portion is disposed between the first portion and the second portion in the first direction. A width of the third portion is smaller than a width of the first portion and a width of the second portion. The distance between the two adjacent active regions may be increased by the third portions accordingly.

Abstract: In various embodiments, etchants featuring (i) mixtures of hydrochloric acid, methanesulfonic acid, and nitric acid, or (ii) mixtures of phosphoric acid, methanesulfonic acid, and nitric acid, are utilized to etch metallic bilayers while minimizing resulting etch discontinuities between the layers of the bilayer.

Abstract: Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.

Abstract: A method for manufacturing a liquid-crystal antenna device is provided. The method includes step (a) providing a first mother substrate. The first mother substrate includes a first region and a second region. The first region has a plurality of first sides. An extension line of at least one of the first sides divides the second region into a first part and a second part. The method also includes the following steps: (b) forming a first electrode layer on the first region and the second region, and (c) cutting the first mother substrate along the first sides of the first region.

Abstract: Techniques are provided to fabricate semiconductor integrated circuit devices which include complementary metal-oxide-semiconductor gate-all-around field-effect transistor devices (e.g., nanosheet field-effect transistor devices), wherein the channel orientation layout of N-type and P-type field-effect transistor devices are independently configured to provide enhanced carrier mobility in the channel layers of the different type field-effect transistor devices.