Patents Examined by Daniel Whalen
  • Patent number: 11462707
    Abstract: A display panel including a substrate, anodes disposed on or above the substrate, light-emitting layers disposed on or above the anodes, a first intermediate layer disposed on or above the light-emitting layers, a second intermediate layer disposed on the first intermediate layer, and a cathode disposed on or above the second intermediate layer. The first intermediate layer includes a fluoride of a first metal or a complex of the first metal. The second intermediate layer includes a second metal. The anodes are light-transmissive and the cathode is light-reflective, or the anodes are light-reflective and the cathode is light-transmissive. The first metal is selected from a group consisting of alkali metals and alkaline earth metals. The second metal is selected from rare earth metals.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: October 4, 2022
    Assignee: JOLED INC.
    Inventors: Hiroshi Katagiri, Takahiro Komatsu
  • Patent number: 11456443
    Abstract: A light emitting structure comprises a substrate, a plurality of sub-pixel stacks over the substrate emitting different colors, a bank surrounding the sub-pixel stacks and forming an interior space above the sub-pixel stacks, a first filler material in the interior space, a second filler material over the first filler material, and an interface between the first filler material and the second filler material. Each of the sub-pixel stacks including an emissive layer between a first transport layer and a second transport layer, a first electrode layer coupled to the first transport layer, and a second electrode layer coupled to the second transport layer. The sub-pixel stacks each have a substantially uniform distance between the emissive layer and the first electrode layer. Each of the sub-pixel stacks emits a main emission peak at one direction normal to a top surface of each of the sub-pixel stacks through the interface.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: September 27, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: David James Montgomery
  • Patent number: 11437362
    Abstract: A multi-cavity package includes a single metal flange having first and second opposing main surfaces. The multi-cavity package also includes a circuit board attached to the first main surface of the single metal flange. The circuit board includes a first surface facing the single metal flange, and a second surface facing away from the first surface. The circuit board also includes a plurality of openings exposing different regions of the first main surface of the single metal flange. The circuit board also includes a lateral extension that overhangs the single metal flange. A corresponding method of manufacturing is also provided.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: September 6, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Saurabh Goel, Alexander Komposch, Cynthia Blair, Cristian Gozzi
  • Patent number: 11430670
    Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Der-Chyang Yeh, Li-Hsien Huang
  • Patent number: 11430651
    Abstract: A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: August 30, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John Zhang
  • Patent number: 11411193
    Abstract: An organic light emitting element includes, in sequence, an anode, a first light emitting layer, a second light emitting layer, and a cathode. The first light emitting layer includes a first compound and a first light emitting material. The second light emitting layer includes a second compound and a second light emitting material having an energy gap different from an energy gap of the first light emitting material. The organic light emitting element satisfies relations (a) to (c). LUMO(H1)>LUMO(D1)??(a) LUMO(H2)>LUMO(D2)??(b) LUMO(H2)?LUMO(D2)>LUMO(H1)?LUMO(D1)??(c) Where LUMO (H1), LUMO (D1), LUMO (H2), and LUMO (D2) represent a LUMO level of the first compound, a LUMO level of the first light emitting material, a LUMO level of the second compound, and a LUMO level of the second light emitting material, respectively.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 9, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hirokazu Miyashita, Itaru Takaya, Naoki Yamada, Isao Kawata, Yuto Ito, Jun Kamatani
  • Patent number: 11410887
    Abstract: The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ying-Keung Leung
  • Patent number: 11404342
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 11398467
    Abstract: A method for forming a semiconductor device includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring, wherein the second guard ring directly contacts the first guard ring. The method further includes forming an isolation structure between the first guard ring and the second guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: July 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Song Sheu, Jian-Hsing Lee, Yu-Chang Jong, Chun-Chien Tsai
  • Patent number: 11393734
    Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 19, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Sung Sun Park, Ji Young Chung, Christopher Berry
  • Patent number: 11393802
    Abstract: According to an aspect of the present disclosure, a stretchable display device includes a lower substrate. A plurality of first substrates is disposed on the lower substrate and includes a plurality of pixels, and a plurality of connection lines electrically connects the plurality of pixels. A plurality of heat transfer lines overlap the plurality of connection lines, and a heat radiator is exposed to the outside and overlaps the plurality of connection lines and the plurality of heat transfer lines. By doing this, a heat radiation efficiency of the stretchable display device may be improved.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: July 19, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Mingyu Kang, KyungChan Kim
  • Patent number: 11373939
    Abstract: Implementations of power modules may include: a substrate having a first side and a second side. The power module may include a plurality of leads coupled to a second side of the substrate and a molding compound over a portion of five or more surfaces of the substrate. The power module may also include an opening extending from a first side of the substrate to an outer edge of the molding compound. The opening may be configured to receive a coupling device and the coupling device may be configured to couple with a heat sink or a package support.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: June 28, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jinchang Zhou, Asif Jakwani, Chee Hiong Chew, Yusheng Lin, Sravan Vanaparthy, Silnore Tejero Sabando
  • Patent number: 11355734
    Abstract: To provide an organic photoelectronic element, of which the external quantum efficiency is improved, the power consumption is low and the service life is prolonged. The organic photoelectronic element comprises a substrate, an anode provided on the substrate, a cathode facing the anode, a light emitting layer disposed between the anode and the cathode, and a hole transport layer provided in contact with the light emitting layer between the light emitting layer and the anode, wherein the hole transport layer contains an organic semiconductor material and a fluorinated polymer, and at the surface of the hole transport layer in contact with the light emitting layer, the fluorinated polymer is present.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: June 7, 2022
    Assignees: AGC Inc., National University Corporation Yamagata University
    Inventors: Takefumi Abe, Yasuhiro Kuwana, Shigeki Hattori, Kaori Tsuruoka, Daisuke Yokoyama
  • Patent number: 11349074
    Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hyun Jeong, Jin-Woo Lee, Gwan-Hyeob Koh, Dae-Hwan Kang
  • Patent number: 11342524
    Abstract: A light-emitting element is provided to improve light emission efficiency of a light-emitting element. The light-emitting element includes: a first electrode; a second electrode; a quantum dot layer provided between the first electrode and the second electrode, in which quantum dots are layered; and a hole-transport layer provided between the quantum dot layer and the first electrode, wherein the hole-transport layer includes a plurality of layers each containing a different material, the plurality of layers of the hole-transport layer each have an ionization potential increasing from the first electrode toward the quantum dot layer, and, among the plurality of layers of the hole-transport layer, a layer in contact with the quantum dot layer is higher in ionization potential than the quantum dot layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 24, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihiro Ueta, Shinichi Handa, Noboru Iwata
  • Patent number: 11329242
    Abstract: A lighting device comprises a substrate including an active area; a first electrode disposed on the substrate and including a transparent conductive material; an organic material layer disposed on the first electrode and including a first light emitting layer and a second light emitting layer; and a second electrode disposed on the organic material layer and including a reflective material, wherein the first light emitting layer emits light having a first wavelength and the second light emitting layer emits light having a second wavelength, and wherein the second light emitting layer includes a first dopant absorbing the light having the first wavelength and emitting the light having the second wavelength.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 10, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jaemin Moon, Jina You, JungHyoung Lee, SunHee Lee, JangDae Youn
  • Patent number: 11322712
    Abstract: An organic light-emitting diode (OLED) structure and a manufacturing method thereof are provided. The OLED structure includes a substrate, a metal layer, a passivation layer, an anode, and an OLED functional layer. By setting the OLED functional layer to form a PN junction with low impedance. The PN junction and a conductive layer with high impedance constitute a resistive divider, and the PN junction is turned on by adjusting a high-voltage direct current (DC) input source and a low-voltage DC input source. Because the resistance of the PN junction is very small, the potential of the cathode can be approximated to the potential of the low-voltage DC input source according to resistive voltage divider rule, and the low-voltage DC input source uses low-resistance metal, which can effectively avoid the problem of IR drop.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: May 3, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Longqiang Shi
  • Patent number: 11322579
    Abstract: A semiconductor device includes a substrate and memory cell arrays arranged on the substrate in a first direction and second direction. The first direction and second direction are parallel to a top surface of the substrate and intersect each other. The memory cell arrays include a plurality of memory cells. A cell dummy pattern on the substrate is arranged between the memory cell arrays in at least one of the first direction and second direction and extends along a side of the memory cell arrays. A cell conductive pattern is included on the substrate. A cell contact plug is configured to connect the cell dummy pattern and the cell conductive pattern. The cell contact plug is arranged between the cell dummy pattern and the cell conductive pattern in a third direction that is perpendicular to the first direction and the second direction.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Song Yi Kim, Junghyun Cho
  • Patent number: 11315961
    Abstract: (Object) To miniaturize a field-effect transistor. (Means of Achieving the Object) A field-effect transistor includes a semiconductor film formed on a base, a gate insulating film formed on a part of the semiconductor film, a gate electrode formed on the gate insulating film, and a source electrode and a drain electrode formed in contact with the semiconductor film, wherein a thickness of the source electrode and the drain electrode is smaller than a thickness of the gate insulating film, and the gate insulating film includes a region that is not in contact with the source electrode or the drain electrode.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: April 26, 2022
    Assignee: Ricoh Company, Ltd.
    Inventors: Sadanori Arae, Yuichi Ando, Yuki Nakamura, Yukiko Abe, Shinji Matsumoto, Yuji Sone, Naoyuki Ueda, Ryoichi Saotome, Minehide Kusayanagi
  • Patent number: 11315839
    Abstract: An evaluation method of a SiC epitaxial wafer includes: a first observation step of preparing a SiC epitaxial wafer having a high-concentration epitaxial layer having an impurity concentration of 1×1018 cm?3 or more, irradiating a surface of the high-concentration epitaxial layer having an impurity concentration of 1×1018 cm?3 or more with excitation light, and observing a surface irradiated with the excitation light via a band-pass filter having a wavelength band of 430 nm or less.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 26, 2022
    Assignee: SHOWA DENKO K.K.
    Inventors: Yoshitaka Nishihara, Koji Kamei