Abstract: A solid-state imaging device includes a first electrode, a second electrode, and a photoelectric conversion film that is formed between the first electrode and the second electrode and includes an organic semiconductor and an inorganic material.

Abstract: A display module and a large format display apparatus incorporating the display module are provided. The display module includes a thin film transistor substrate, light emitting diodes arranged on one surface of the thin film transistor substrate, and side wirings formed on each of a first edge of the thin film transistor substrate and a second edge of the thin film transistor substrate that is adjacent to the first edge, to electrically couple components on the one surface of the thin film transistor substrate with components on an opposite surface of the one surface respectively.

Abstract: A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated into a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A first logic device comprises a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed on the first logic gate dielectric within the logic device trench. By arranging the first logic gate electrode within the logic device trench, metal layer loss and the resulted sheet resistance and threshold voltage variations and mismatch issues caused by the subsequent planarization process can be improved.

Abstract: A variable resistance memory device may include a memory unit including a first electrode disposed on a substrate, a variable resistance pattern disposed on the first electrode and a second electrode disposed on the variable resistance pattern, a selection pattern disposed on the memory unit, and a capping structure covering a sidewall of the selection pattern. The capping structure may include a first capping pattern and a second capping pattern sequentially stacked on at least one sidewall of the selection pattern. The first capping pattern may be silicon pattern, and the second capping pattern may include a nitride.

Abstract: A thin film transistor includes an active layer including a channel portion; a gate electrode spaced apart from the active layer and overlapping at least a part of the active layer; and source and drain electrodes connected with the active layer and spaced apart from each other, wherein the channel portion includes, a first boundary portion connected with one of the source and drain electrodes; a second boundary portion connected with the other one of the source and drain electrodes; and a main channel portion interposed between the first boundary portion and the second boundary portion, and wherein at least a part of the second boundary portion has a thickness smaller than a thickness of the main channel portion.

Abstract: An organic light-emitting display apparatus including a substrate, a first first electrode on the substrate, a first organic functional layer on the first first electrode, the first organic functional layer including a first emission layer, a first second electrode on the first organic functional layer, a second first electrode on the substrate, the second first electrode being spaced apart from the first first electrode, a second organic functional layer on the second first electrode, the second organic functional layer including a second emission layer, a second second electrode on the second organic functional layer, and a self-assembled layer between the first organic functional layer and the second organic functional layer, the self-assembled layer containing fluorine.

Abstract: A semiconductor device includes an n-type base substrate; a p-type first region; a p-type surface region having a plurality of second corner portions and a plurality of second side portions surrounding the first region. The p-type surface region has a dopant concentration lower than a dopant concentration of the first region. The semiconductor device further includes a field plate in a region overlapping with the surface region in a plan view by way of an insulation film. The field plate has a plurality of field plate corner portions and a plurality of field plate side portions. A relationship of L1>L2 is established at least at a portion of the surface region or a relationship of FP1>FP2 is established at least at a portion of the field plate is satisfied. A withstand voltage of the second side portion is lower than a withstand voltage of the second corner portion.

Abstract: A display panel and a display device includes a high-permittivity material disposed between electrodes of capacitor disposed in a subpixel. This increases the capacitance per area of the capacitor, such that a high-resolution display device is provided. A high-permittivity material is disposed in the insulating layer, and the surface of the insulating layer is planarized by polishing. The high-permittivity material is prevented from residing in any area, except for the area in which the capacitor is disposed. An unnecessary increase in load in the subpixel is prevented, and the capacitance of the capacitor is increased.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric structure disposed over a substrate. A plurality of conductive interconnect layers are disposed within the dielectric structure. The plurality of conductive interconnect layers include alternating layers of interconnect wires and interconnect vias. A metal-insulating-metal (MIM) capacitor is arranged within the dielectric structure. The MIM capacitor has a lower conductive electrode separated from an upper conductive electrode by a capacitor dielectric structure. The MIM capacitor vertically extends past two or more of the plurality of conductive interconnect layers.

Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, where the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, forming multiple sets of stepped surfaces in terrace regions of the vertically alternating sequence, forming memory stack structures through memory array regions of the vertically alternating sequence, and forming a metal interconnect structure which electrically connects a portion of a topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region, and which extends above a horizontal plane of the topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region.

Abstract: An organic light-emitting display apparatus including a substrate, a first first electrode on the substrate, a first organic functional layer on the first first electrode, the first organic functional layer including a first emission layer, a first second electrode on the first organic functional layer, a second first electrode on the substrate, the second first electrode being spaced apart from the first first electrode, a second organic functional layer on the second first electrode, the second organic functional layer including a second emission layer, a second second electrode on the second organic functional layer, and a self-assembled layer between the first organic functional layer and the second organic functional layer, the self-assembled layer containing fluorine.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions.

Abstract: There is provided a solid-state imaging device including: one or more photoelectric conversion elements provided on side of a first surface of a semiconductor substrate; a through electrode coupled to the one or more photoelectric conversion elements, and provided between the first surface and a second surface of the semiconductor substrate; and an amplifier transistor and a floating diffusion provided on the second surface of the semiconductor substrate, in which the one or more photoelectric conversion elements are coupled to a gate of the amplifier transistor and the floating diffusion via the through electrode.

Abstract: A phosphor according to an embodiment is a europium-activated alkaline-earth chloroapatite phosphor having a composition expressed by a composition formula: (M1-xEux)5(PO4)3Cl, where M is an alkaline-earth element containing at least Sr and Ba, x is an atomic ratio satisfying 0.04?x?0.2. In the phosphor of this embodiment, absorptance of light at a wavelength of 400 nm is 90% or more, and absorptance of light at a wavelength of 650 nm is 2% or less.

Abstract: A high degree of phase difference detection accuracy can be obtained using a phase difference pixel with a simpler configuration. A solid-state image-capturing device includes a pixel array unit in which a plurality of pixels including a phase difference pixel which is a pixel for focal point detection and an image-capturing pixel which is a pixel for image generation are arranged in a two-dimensional array. In this case, a predetermined layer between a light shielding layer and a micro lens formed in the image-capturing pixel has a higher refraction index than a refraction index of the predetermined layer formed in the phase difference pixel. The technique of the present disclosure can be applied to, for example, a back-illuminated-type solid-state image-capturing device and the like.

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and distal regions proximate the control gate regions. The control gate regions have front surfaces, top surfaces and bottom surfaces. The top and bottoms surfaces extend back from the front surfaces. High-k dielectric material is along the control gate regions. The high-k dielectric material has first regions along the top and bottom surfaces, and has second regions along the front surfaces. The first regions are thicker than the second regions. Charge-blocking material is adjacent to the second regions of the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. Gate-dielectric material is adjacent to the charge-storage material. Channel material is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies.

Abstract: An electro-optical device includes a base material as a substrate, a TFT as a transistor, a scanning line as a light shielding layer between the base material and the TFT, and a holding capacitor between the base material and the scanning line. The holding capacitor includes a first conductive layer, a second conductive layer provided on the first conductive layer via a first capacitor insulating layer, a third conductive layer electrically connected to the second conductive layer via a first contact hole provided in an insulating layer covering the second conductive layer, and a fourth conductive layer provided on the third conductive layer via a second capacitor insulating layer.

Abstract: A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.