Patents Examined by David A. Hey
  • Patent number: 4645546
    Abstract: Disclosed is a silicon semiconductor substrate for a semiconductor integrated circuit such as LSI or VLSI. The silicon semiconductor substrate has an oxygen concentration ranging from 3.times.10.sup.17 cm.sup.-3 to 7.times.10.sup.17 cm.sup.-3 and a gettering layer on its backside. This gettering layer may comprise a nonsingle crystalline silicon layer such as polycrystalline silicon layer or amorphous silicon layer, or a layer having stacking fault density of more than 3.times.10.sup.4 cm.sup.-2.
    Type: Grant
    Filed: July 12, 1985
    Date of Patent: February 24, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Matsushita
  • Patent number: 4642880
    Abstract: A method for manufacturing a semiconductor device comprises a first step of forming a field insulation layer on a p-type semiconductor substrate and a second step of forming an n.sup.+ -type region and n-type region in an element area surrounded by the field insulation layer. In particular, the second step includes a step of forming, in the element area, a recess having an inclined portion and flat bottom portion, a step of forming an SiO.sub.2 film of a uniform thickness on the inclined portion and flat bottom portion, and a step of ion-implanting an n-type impurity into the substrate through the SiO.sub.2 and effecting an annealing process.
    Type: Grant
    Filed: April 17, 1985
    Date of Patent: February 17, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihisa Mizutani, Syunzi Yokogawa
  • Patent number: 4642144
    Abstract: A method of doping amorphous semiconductor films have a first bandgap by forming the first bandgap amorphous material in a first plurality of spaced apart layers; and then forming a second plurality of semiconductor layers of amorphous material having a second bandgap wider than the first bandgap interleaved with and contiguous with the first plurality such that the conductor and valence band step at the interfaces between the first plurality and the second plurality is of sufficient magnitude to confine carriers. The second plurality is doped such that the electrons in the gap states from the second plurality of layers transfer to the first plurality of layers and cause the conductivity of said first plurality to increase.
    Type: Grant
    Filed: October 6, 1983
    Date of Patent: February 10, 1987
    Assignee: Exxon Research and Engineering Company
    Inventors: Thomas J. Tiedje, Benjamin Abeles
  • Patent number: 4638551
    Abstract: An improved Schottky barrier device and method of manufacture is disclosed. The device has a semiconductor layer of first conductivity type; an insulating layer covering one face of the semiconductor layer, and has an opening therein. A conductor layer covers the semiconductor layer where the semiconductor layer is exposed by the opening and there forms a recitifying junction with the semiconductor layer. A first region of opposite conductivity type is at the one face of semiconductor layer and extends from where the conductor layer meets the insulating layer and below the conductor layer. A second region of opposite conductivity type is at the one face of semiconductor layer and begins where the conductor layer meets the insulating layer and extending below the insulating layer.
    Type: Grant
    Filed: February 21, 1985
    Date of Patent: January 27, 1987
    Assignee: General Instrument Corporation
    Inventor: Willem G. Einthoven
  • Patent number: 4637128
    Abstract: A method of producing a semiconductor device comprises an isolation step for forming an n-type region in contact with p.sup.+ -type source and drain regions of a p-channel floating gate MOS transistor in the surface area of an n-type semiconductor substrate and an n.sup.+ -type region in contact with the n-type region. In this isolation step, and oxidation resistant film pattern is formed on the element region of the MOS transistor. An anisotropic etching is applied to the substrate with the oxidation resistant film pattern used as a mask to form an inclined portion and a flat portion, followed by forming a SiO.sub.2 film of a prescribed thickness to cover both the inclined and flat portions. Further, an n-type impurity is introduced by ion implantation into the substrate through the SiO.sub.2 film in a direction perpendicular to the flat portion, followed by annealing the ion-implanted region.
    Type: Grant
    Filed: April 23, 1985
    Date of Patent: January 20, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa Mizutani
  • Patent number: 4633573
    Abstract: A microcircuit package and sealing method in which a non-organic coating is used to hermetically seal the microcircuit. The microcircuit is isolated and insulated in order to protect the microcircuit from the high temperatures required to apply and cure a non-organic coating. The materials and methods used to isolate and insulate the microcircuit are chosen so that the thermal coefficients of the materials are complementary and thus form a highly reliable, durable seal, while also insulating the microcircuit during the process of applying the non-organic coating.
    Type: Grant
    Filed: May 23, 1984
    Date of Patent: January 6, 1987
    Assignee: Aegis, Inc.
    Inventor: Jeremy D. Scherer
  • Patent number: 4631806
    Abstract: Method of producing two-layer metal interconnections in a semiconductor integrated circuit structure coated with silicon dioxide. Masking material is deposited on the silicon dioxide. Openings are formed in the masking material and then in the silicon dioxide to expose contact areas on the integrated circuit structure. A first metal, tungsten, is deposited on the masking material and on the contact areas exposed at the openings. The masking material and the overlying tungsten are stripped off leaving tungsten only on the contact areas. A second metal, aluminum, is deposited over the silicon dioxide and the tungsten on the contact areas. Aluminum is selectively removed to form a pattern of conductive members of tungsten-aluminum on the contact areas and of aluminum over the silicon dioxide.
    Type: Grant
    Filed: May 22, 1985
    Date of Patent: December 30, 1986
    Assignee: GTE Laboratories Incorporated
    Inventors: Paul E. Poppert, Marvin J. Tabasky, Eugene O. Degenkolb
  • Patent number: 4630355
    Abstract: Circuit assemblies are disclosed which include a supporting substrate, a plurality of conductive lines supported on the substrate and a deposited phase-change material capable of an energy induced phase change from an initially high resistance state to a relatively low resistance state placed in electrical contact with the conductive lines. The assemblies also include contact receiving means connected to the conductive lines at preselected discrete locations to receive externally applied contact means, such as electric probes, for applying voltages across selected portions of the conductive lines. The application of such voltages can induce a phase change in portions of the phase-change material which bridge breaks in the conductive lines of such circuit subassemblies, changing such portions from their high resistance state to their low resistance state, thereby forming electrically shunting conductive paths around such open circuits. There are also disclosed methods of making such circuit assemblies.
    Type: Grant
    Filed: March 8, 1985
    Date of Patent: December 23, 1986
    Assignee: Energy Conversion Devices, Inc.
    Inventor: Robert R. Johnson
  • Patent number: 4627151
    Abstract: A system for the assembly and packaging of integrated circuits employs circuit dice that have contact pads in a standard array; a leadframe having leads configured to have the same spring constant; a method for removing selected dice from a wafer array under computer control; and a method of simultaneously bonding all leads to the die.
    Type: Grant
    Filed: March 22, 1984
    Date of Patent: December 9, 1986
    Assignee: Thomson Components-Mostek Corporation
    Inventors: Wayne A. Mulholland, Daniel J. Quinn, Robert H. Bond, Michael A. Olla
  • Patent number: 4625391
    Abstract: A method of forming electric conductive patterns comprising the steps of forming first conductive patterns on a semiconductor substrate directly or through an insulating layer with first insulating film being formed thereon, selectively forming second conductive patterns, forming insulation layers on side surfaces of said second conductive patterns, thereby electrically insulating said second conductive patterns from said first conductive patterns through said insulation layers in a self-aligned manner. An semiconductor device having electric conductive patterns formed by above-mentioned method.
    Type: Grant
    Filed: June 18, 1982
    Date of Patent: December 2, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Yoshitaka Sasaki
  • Patent number: 4624047
    Abstract: A method for fabricating isolated regions for a dielectric isolated complementary integrated circuit which avoids the difficulty of mask alignment and patterning on a deeply etched uneven surface of the substrate by aligning the patterns before etching and thereby forming p-type and n-type islands at the same time. A poly-silicon layer is grown on the surface of the substrate covering the islands and the substrate is removed from its back surface, leaving the islands embedded in the poly-silicon layer which becomes a new substrate.
    Type: Grant
    Filed: October 11, 1984
    Date of Patent: November 25, 1986
    Assignee: Fujitsu Limited
    Inventor: Satoru Tani
  • Patent number: 4622736
    Abstract: A Schottky barrier diode is made from a substrate of semiconductor material by forming, on a major surface of the wafer, a layer of dielectric material defining a restricted opening through which the semiconductor material is exposed. A metal which forms with the semiconductor material a single phase compound which is inherently stable at temperatures up to 600 deg. C. is deposited into the opening, into contact with the exposed semiconductor material. By heating the substrate and the metal deposited thereon, the metal reacts with the semiconductor material to form a body of the single phase compound. A layer of refractory metal which reacts with the dielectric material is deposited over the dielectric material and the body of single phase compound.
    Type: Grant
    Filed: January 30, 1984
    Date of Patent: November 18, 1986
    Assignee: Tektronix, Inc.
    Inventor: Vladimir F. Drobny
  • Patent number: 4615865
    Abstract: Improved coating compositions are described for the protection of superalloys at elevated temperatures. The coatings of the NiCrAlY or NiCoCrAlY type are significantly improved by the use of higher levels of yttrium.
    Type: Grant
    Filed: July 12, 1983
    Date of Patent: October 7, 1986
    Assignee: United Technologies Corporation
    Inventors: David S. Duvall, Dinesh K. Gupta
  • Patent number: 4613885
    Abstract: A high-voltage CMOS process, providing (for 5 micron geometries) both field thresholds and junction breakdowns in excess of 20 volts, wherein only one channel stop implant is used. A double-well process in an epitaxial structure is used. Phosphorus is preferably used as the dopant for the N-tank, and boron is used for the blanket channel stop implant. The boron tends to leach into oxide, and the phosphorus tends to accumulate at the surface, and a high field threshold is achieved over both PMOS and NMOS regions.
    Type: Grant
    Filed: January 12, 1984
    Date of Patent: September 23, 1986
    Assignee: Texas Instruments Incorporated
    Inventor: Roger A. Haken
  • Patent number: 4611386
    Abstract: A method of producing a semiconductor device having an isolation region between elements. Each element is surrounded by a field oxide film, and is isolated by the dielectric isolation structure of a groove filled with an insulating material. The field oxide film is formed by selectively oxidizing an epitaxial layer, and the groove extending through the epitaxial layer and a buried layer is formed after the oxidation of the epitaxial layer. After the surface of the groove is covered with an insulating film, e.g., a thermal oxide film created by oxidizing the surface, the groove is filled with insulating filler material.
    Type: Grant
    Filed: December 23, 1983
    Date of Patent: September 16, 1986
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Goto
  • Patent number: 4611389
    Abstract: A semiconductor device package structure having a conventional base outline, a heat spreader, and top-mounted, quick-connect terminals for external connection is described. A pre-packaged semiconductor device is attached to a lead frame containing terminals in a predetermined configuration, and then overmolded with a plastic encapsulant so that the heat spreader of the prepackaged device protrudes a predetermined distance from the mounting surface of the package to make possible good thermal contact with a heat sink. Insulated means to facilitate mounting are built-in.
    Type: Grant
    Filed: March 18, 1985
    Date of Patent: September 16, 1986
    Assignee: Motorola, Inc.
    Inventors: Kelvin R. Blair, Lynn C. Furman, David M. Knott
  • Patent number: 4608749
    Abstract: A method of manufacturing a "two-level" solid-state image pickup device wherein a portion of a first metallic electrode electrically connected to a signal storage region is made to project to the highest position above a substrate on which it is formed. A coating of an organic insulating film is then applied to produce a flat surface. The entire surface of the organic film is then etched to expose the projections of the first metallic electrode. A second metallic electrode constituting a pixel electrode is connected to the first electrode at the exposed portion thereof.
    Type: Grant
    Filed: August 22, 1984
    Date of Patent: September 2, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nozomu Harada, Yoshiaki Komatsubara
  • Patent number: 4608097
    Abstract: A method is described for producing an electronically passivated stable surface on silicon wafers. The passivation technique consists of first fluorinating the surface of a crystalline silicon wafer under inert atmospheric conditions. Such a treatment may consist of either a vapor phase or liquid phase application of HF at room temperature. The surface fluorinated wafer is then maintained in an inert atmosphere and a thin coating of an organic solid is applied to the wafer which does not disturb the underlying passivated silicon surface. The wafer may then be further processed into a variety of different devices.
    Type: Grant
    Filed: October 5, 1984
    Date of Patent: August 26, 1986
    Assignee: Exxon Research and Engineering Co.
    Inventors: Bernard R. Weinberger, Harry W. Deckman, Eli Yablonovitch
  • Patent number: 4608095
    Abstract: Semiconductor substrate materials, such as silicon, useful in the manufacture of electronic devices, such as integrated circuits, employing low temperature, i.e., below 1025.degree. C. processing cycles are provided with a 0.05 to 2.0 micron thick layer of polysilicon on the backside to improve gettering capabilities of defects, contaminants and impurities away from the active device region of the substrate.
    Type: Grant
    Filed: April 4, 1985
    Date of Patent: August 26, 1986
    Assignee: Monsanto Company
    Inventor: Dale E. Hill
  • Patent number: 4608096
    Abstract: Semiconductor substrate materials, such as silicon, useful in the manufacture of electronic devices, such as integrated circuits, employing low temperature, i.e., below 1025.degree. C. processing cycles are provided with a 0.05 to 2.0 micron thick layer of polysilicon on the backside to improve gettering capabilities of defects, contaminants and impurities away from the active device region of the substrate.
    Type: Grant
    Filed: June 28, 1985
    Date of Patent: August 26, 1986
    Assignee: Monsanto Company
    Inventor: Dale E. Hill