Patents Examined by David A. Hey
  • Patent number: 4569122
    Abstract: A fabrication method and resulting integrated circuit structure that provide a second level of interconnect, a low resistance contact strap between underlying layers which is not sensitive to alignment and low lateral diffusion polysilicon load. The method comprises the steps of providing contact openings in an insulating layer on a wafer to any desired underlying circuit layers, depositing a silicide layer on the wafer, removing selected portions of the silicide layer, depositing a polysilicon layer on the wafer, lightly doping the polysilicon layer to a level appropriate for the resistor, and then removing portions of the polysilicon along with underlying silicide.
    Type: Grant
    Filed: March 9, 1983
    Date of Patent: February 11, 1986
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Hugo W. K. Chan
  • Patent number: 4567643
    Abstract: The subject matter of the invention is a method of substituting an electronic component (A1) for an analogous component (1) connected to the conductive tracks (3) of a support substrate (2) by connection wires (4). The conductive tracks are cut beyond, relative to the component (1) to be taken out of service, the zones where the connection wires (4) are connected to the tracks, then the replacement component (A1) is placed on the upper glued face of the component (1), and is connected to the tracks by connection wires (4A) independent from the preceding wires.This invention is particularly applicable to integrated circuits and to vacuum-deposited resistive thin film circuits.
    Type: Grant
    Filed: December 3, 1984
    Date of Patent: February 4, 1986
    Assignee: Sintra-Alcatel
    Inventors: Jean-Paul Droguet, Michel Vernay, Gerard Teissier
  • Patent number: 4566177
    Abstract: Electromigration resistance of aluminum alloy conductors in semiconductor devices is found to significantly increase by rapidly annealing the conductors by employing an annealing cycle with a peak temperature of C. and a cycle time of about 5 to 30 seconds such as is developed by high intensity CW lamps.
    Type: Grant
    Filed: May 11, 1984
    Date of Patent: January 28, 1986
    Assignee: Signetics Corporation
    Inventors: Everhardus P. G. T. van de Ven, Janet M. Towner
  • Patent number: 4566173
    Abstract: The method in accordance with the invention is used for the production of field-effect transistors and preferably implemented in such a manner that a thin aluminum layer (2) is deposited on the surface of a silicon substrate (1), for example, by means of a basic cleaning solution containing aluminum, that subsequently thermal oxidation is effected, during which, in addition to a silicon dioxide layer (3), an about 1 to 1.5 nm thick layer (4) containing aluminum oxide and silicon dioxide is formed and that finally, if required, at least one further layer, for example, an Si.sub.3 N.sub.4 (5) or an Si.sub.3 N.sub.4 (5) and an SiO.sub.2 layer are deposited. By adding about 400 ppb aluminum to the cleaning solution, which in the finished structure equals a quantity of aluminum of about 250 pg/cm.sup.2 layer surface, the threshold voltage V.sub.S is raised by about 470 millivolts.
    Type: Grant
    Filed: June 4, 1982
    Date of Patent: January 28, 1986
    Assignee: International Business Machines Corporation
    Inventors: Werner Gossler, Anneliese Strube, Manfred Zurheide
  • Patent number: 4564997
    Abstract: A semiconductor device in which a film of an insulator a conductor is closely deposited in a groove formed in a semiconductor substrate or an insulating or conductor layer thereon to planarize the surface thereof.A semiconductor device manufacturing process in which a specimen is selectively etched away through using a resist pattern as a mask, a pattern forming film is deposited by a plasma deposition technique on the specimen, and the resist film is removed, whereby the pattern forming film closed fills up a groove formed by etching to provide a planarized surface.
    Type: Grant
    Filed: April 16, 1982
    Date of Patent: January 21, 1986
    Assignee: Nippon-Telegraph and Telephone Public Corporation
    Inventors: Seitaro Matsuo, Susumu Muramoto, Kohei Ehara, Manabu Itsumi
  • Patent number: 4558508
    Abstract: A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implantation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers.
    Type: Grant
    Filed: October 15, 1984
    Date of Patent: December 17, 1985
    Assignee: International Business Machines Corporation
    Inventors: Wayne I. Kinney, Charles W. Koburger, III, Jerome B. Lasky, Larry A. Nesbit, Ronald R. Troutman, Francis R. White
  • Patent number: 4558507
    Abstract: The present invention relates to a method of forming a diffused region with a shallow junction having a refractory metal silicide layer thereon. At first, the refractory metal silicide layer is selectively formed on a silicon substrate of one conductivity type. An insulating film is then formed at least on the refractory metal silicide layer, and a contact hole is opened on a part of the silicide layer. After necessary high temperature treatments have been conducted, a dopant impurity of the opposite conductivity type is introduced from the contact hole to the silicide layer. The impurity is laterally dispersed in the silicide layer and diffused into the whole portion of the silicon substrate in contact with the silicide layer, whereby the diffused region with a shallow junction can be formed.
    Type: Grant
    Filed: November 10, 1983
    Date of Patent: December 17, 1985
    Assignee: NEC Corporation
    Inventors: Hidekazu Okabayashi, Mitsutaka Morimoto, Eiji Nagasawa
  • Patent number: 4557036
    Abstract: A multilayer structure comprising a Si layer/ a refractory metal oxide layer/ a refractory metal layer/ is subjected to annealing in an atmosphere of hydrogen or an inert gas mixed with hydrogen, thereby converting the multilayer structure into a multilayer structure comprising a Si layer/an inner SiO.sub.2 layer formed by internal oxidation of Si/a refractory metal layer. The inner SiO.sub.2 layer is selectively formed only on the surface of the refractory metal layer, since Si is internally oxidized from the side of the refractory metal layer. In case of gate electrode of a MISFET, the gate electrode and a contact hole for source or drain electrode are positioned in self-alignment with each other via the inner SiO.sub.2 layer. The distance between the gate electrode and the source or drain electrode is determined by the thickness of the inner SiO.sub.2 layer. A semiconductor device with a high density and a high speed is realized.
    Type: Grant
    Filed: March 25, 1983
    Date of Patent: December 10, 1985
    Assignee: Nippon Telegraph & Telephone Public Corp.
    Inventors: Hakaru Kyuragi, Hideo Oikawa
  • Patent number: 4554728
    Abstract: The method of planarizing polysilicon-filled trenches involves first filling the trenches with an undoped polysilicon until the upper surface is substantially planar. The polycrystalline silicon is then heavily doped by means of diffusion of a dopant from the upper surface. The time and temperature of the diffusion are carefully controlled providing for the dopant to penetrate the polysilicon to a depth level with the tops of the trenches. A selective etchant is then utilized which removes the heavily doped polysilicon and leaves the undoped polysilicon untouched in the trenches.
    Type: Grant
    Filed: June 27, 1984
    Date of Patent: November 26, 1985
    Assignee: International Business Machines Corporation
    Inventor: Joseph F. Shepard
  • Patent number: 4553315
    Abstract: The contact for N channel devices in a CMOS process is formed by ion implanting N-type impurities through contact apertures in the dielectric layer to a depth less than the source and drain regions and a layer of conductive material is applied without intermediate etching and delineated.
    Type: Grant
    Filed: April 5, 1984
    Date of Patent: November 19, 1985
    Assignee: Harris Corporation
    Inventor: Chris McCarty
  • Patent number: 4553316
    Abstract: A MESFET is fabricated using a self-aligned gate process. This process uses a vertical (anisotropic) etch to self-align the gate and source/drain. The vertical etch, in conjunction with a two-level insulator, creates a barrier between the gate and source/drain, so that when metal is deposited and reacted, and any excess removed, the gate is selfaligned with the source/drain, and contacts to the source/drain and gate are well isolated. The alignment obtained by this process is advantageous in that series channel resistance is reduced, and a more compact structure is attained for improvement in packing density.
    Type: Grant
    Filed: March 12, 1984
    Date of Patent: November 19, 1985
    Assignee: Texas Instruments Incorporated
    Inventors: Theodore W. Houston, Al F. Tasch, Jr., Henry M. Darley, Horng S. Fu
  • Patent number: 4551910
    Abstract: A process for growing field oxide regions in an MOS circuit. An initial thermally grown layer of silicon nitride seals the substrate surface and reduces lateral oxidation, or bird's beak formation along the substrate-nitride interface. Field oxidation takes place in two steps, with the first step being a dry oxidation in HCL and the second taking place in steam.
    Type: Grant
    Filed: November 27, 1984
    Date of Patent: November 12, 1985
    Assignee: Intel Corporation
    Inventor: Elizabeth L. Patterson
  • Patent number: 4551904
    Abstract: A field-effect transistor (FET) and a corresponding method for its fabrication, the transistor having a source and a gate located at opposite faces of an active channel region formed in a substrate, the source being substantially shorter in effective length than the gate and located symmetrically with respect to the gate. The transistor also has two drains, located one at each end of the channel region, and charge carriers flow from the source to the drains in two paths, under control of the same gate. Electrical contact with the source is made from beneath the substrate, while contact with the gate and drains is made from above. The resulting device has a large incremental transconductance and relatively small parasitic impedances, and therefore can operate at much higher frequencies than conventional FET's.
    Type: Grant
    Filed: June 11, 1984
    Date of Patent: November 12, 1985
    Assignee: TRW Inc.
    Inventors: John J. Berenz, G. Conrad Dalman, Charles A. Lee
  • Patent number: 4551911
    Abstract: A method for manufacturing a semiconductor device which comprises the steps of forming a first groove in that portion of a semiconductor substrate where an isolation is to be formed; selectively forming a second groove narrower than the first groove in that surface region of the semiconductor substrate which is surrounded by said first groove; depositing a masking material over the whole surface of the semiconductor substrate with a thickness less than half the width of the first groove and greater than half the width of the second groove; aniotropically etching the deposited masking material to eliminate substantially its thickness, thus leaving the masking material on the side walls of the first groove and entirely in the second groove; introducing an impurity into the bottom of the first groove to form an impurity region; filling the first groove with an isolating material; and forming a semiconductor element in that section of the semiconductor substrate which is surrounded by an isolation consisting of t
    Type: Grant
    Filed: December 16, 1983
    Date of Patent: November 12, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Gen Sasaki, Shuichi Kameyama
  • Patent number: 4551907
    Abstract: A metal silicide interconnection technique selectively forming a metal silicide layer on a silicon layer followed by heat treating the layers so that a surface silicon dioxide layer is formed and the metal silicide layer is forced down and is buried under the silicon dioxide layer. This silicon dioxide layer has an even top surface.
    Type: Grant
    Filed: November 23, 1983
    Date of Patent: November 12, 1985
    Assignee: Fujitsu Limited
    Inventor: Ryoichi Mukai
  • Patent number: 4546536
    Abstract: The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region.
    Type: Grant
    Filed: August 4, 1983
    Date of Patent: October 15, 1985
    Assignee: International Business Machines Corporation
    Inventors: Narasipur G. Anantha, Jacob Riseman, Paul J. Tsang
  • Patent number: 4546540
    Abstract: This specification discloses a self-aligned manufacturing method of a Schottky gate FET. This method comprises the steps: forming a gate metallic layer on a semiconductor substrate and a mask overhanged on the metallic layer; ion-implanting impurity ions into the semiconductor substrate using the mask to form a source/drain region; depositing an insulator on the gate metallic layer side surface and the other surface below the mask; directionally etching said deposited insulator using the mask to expose the source/drain region; depositing a source/drain electrode using the mask; and removing the mask.
    Type: Grant
    Filed: September 13, 1983
    Date of Patent: October 15, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Kiichi Ueyanagi, Yasunari Umemoto, Susumu Takahashi, Michiharu Nakamura
  • Patent number: 4545112
    Abstract: An improved method of manufacturing thin film transistors. A gate metal is patterned to form a gate electrode and a drain, gate and source contact pad for the transistor. To reduce shorts and capacitance between the gate and the source or the drain, an intermetal dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges.
    Type: Grant
    Filed: August 15, 1983
    Date of Patent: October 8, 1985
    Assignee: Alphasil Incorporated
    Inventors: Scott H. Holmberg, Richard A. Flasck
  • Patent number: 4545610
    Abstract: A process for forming elongated solder terminals to connect a plurality of pads on a semiconductor device to a corresponding plurality of pads on a supporting substrate by,forming a means to maintain a predetermined vertical spacing between the semiconductor and the supporting substrate outside the area of the pads,forming and fixing solder extenders to each of the solder wettable pads on the substrate or the device to be joined,positioning the semiconductor device provided with solder mounds on the solder mountable pads over the supporting substrate with the solder mound in registry and with the pads on the substrate with the solder extenders positioned therebetween, the means to maintain vertical spacing located between and in abutting relation to the device and substrate, andheating the resulting assembly to reflow the solder mounds and the solder extenders while maintaining a predetermined spacing thus forming a plurality of hour-glass shaped elongated connections.
    Type: Grant
    Filed: November 25, 1983
    Date of Patent: October 8, 1985
    Assignee: International Business Machines Corporation
    Inventors: Mark N. Lakritz, Jose Ordonez, Peter J. Tubiola
  • Patent number: 4542577
    Abstract: A submicron conductor is formed by placing a metal member over an insulator both terminating at a common defined edge. An angularly deposited metal against the edge provides a broad metal conductor attached along the entire edge of a thin metal member which is positioned on the substrate on a narrow line with the width defined by the horizontal component of the angular deposition. A removal operation removes with respect to the vertical component of the angular deposition the excess angularly deposited metal and leaves a vertical, very narrow metal conductor having a horizontal metal over the dielectric in electrical and supporting contact along the entire length. The asymmetry of the conductor provides field effect transistor advantages.
    Type: Grant
    Filed: February 23, 1984
    Date of Patent: September 24, 1985
    Assignee: International Business Machines Corporation
    Inventor: Thomas N. Jackson