Abstract: A silicon wafer having a tungsten and/or molybdenum film formed on its surface is heat-treated in hydrogen containing water vapor. Thus, silicon can be selectively oxidized without substantially oxidizing tungsten and/or molybdenum.

Abstract: This transistor comprises a first main surface of alternating source and gate strips. A gate metallization rests on the gate strips and a source metallization rests on a polycrystalline silicon rail formed above the source strips. Such a device can be manufactured by entirely self-aligned methods and is applicable particularly to the very high frequency range up to a few dozen gigahertz.

Abstract: A method for manufacturing a semiconductor device is disclosed which comprises the step of forming one or more first grooves by selectively etching a field region of a semiconductor substrate, the step of forming, on the entire surface of the substrate including the first groove, a first insulating film having a thickness substantially equal to or greater than the depth of the first groove, this first insulating film having on its upper surface one or more second grooves corresponding to the first groove, at least one of the second grooves having a width greater than its depth, the step of selectively forming, in at least one of the second grooves having a width greater than its depth, a second insulating film having a thickness substantially equal to the depth of the second groove, the step of forming a third insulating film having a flat surface on its whole surface, the step of applying an anisotropic dry etching technique to the resultant structure to expose the surface of the substrate, thereby obtaining

Abstract: Process for the positioning of an interconnection line on an electrical contact hole of an integrated circuit, wherein, when the electrical contact hole has been produced, the following stages are performed:deposition of a conductive layer in which the interconnection line is to be formed on the complete integrated circuit;deposition on the conductive layer of an insulating layer blanking the relief thereof and having a planar surface,etching the insulating layer, so that insulating material is only left at the location of the electrical contact hole,deposition of a resin layer on the integrated circuit, so as to mask the interconnection line to be produced,etching of that part of the conductive layer which is free from resin and the residual insulating layer, andelimination of the remaining insulating layer and the resin layer.The positioning process is particularly used in processes for producing MOS integrated circuits.

Abstract: A conductor layer is formed on an insulating film which is formed on a semiconductor substrate and which consists of a thick portion and a thin portion with a step therebetween. A film made of material having an etch rate substantially equal to that of the material of the conductor layer is formed on the layer. The film, which has a substantially flat upper surface, and the conductor layer form a laminated structure. Those portions of the laminated structure which are on the thin portion of the insulating film and said step have substantially the same thickness. A mask layer of a predetermined pattern is formed on the laminated structure. Using the mask layer, the laminated structure is selectively etched, the selected portions of the conductor layer and film being etched at the same etching rate. Thereafter, the mask layer and the remaining film are removed.

Abstract: A semiconductor device having particularly low resistance connection to a portion thereof carrying substantial current is described. First and second electrodes are provided on a major surface of the semiconductor, the first electrode providing lateral contact to a control region of the semiconductor device; the second electrode providing low impedance vertical contact to the high current carrying region. A conductive plate is supported between upstanding spaced apart portions of the second electrode and is thereby vertically spaced apart from the first electrode.

Abstract: A method of forming a number of discrete solder layers on a semiconductor wafer of a large area. A number of regions which are easy to be wetted with solder are formed on one of the major surfaces of the wafer. A solder foil is positioned on the one major surface and a plate-like jig including a plate and projections formed on one surface thereof is disposed on the solder foil with the projections facing the latter. By heating the stacked assembly at a sufficiently high temperature for the solder foil to be molten, a number of the discrete solder layers having a uniform thickness are formed on the semiconductor wafer.

Abstract: A semiconductor device is manufactured by selectively removing an insulating film which covers at least one conductive layer to form at least one contact hole partially exposing the conductive layer. Then, a layer of an inorganic conductive material having a melting point lower than the material comprising the conductive layer is formed on a surface of the insulating film and is melted to fill the contact hole with the inorganic conductive material. Finally a wiring layer is formed in contact with the inorganic conductive material filled in the contact hole.

Abstract: A wiring material of a semiconductor device, which comprises aluminum as a major component and at least a surface layer of the wiring layer is alloyed with boron and silicon. A method for forming a wiring material of a semiconductor device, which comprises the steps of: forming a wiring pattern comprising aluminum as a major component on a semiconductor element; and ion-implanting one of boron and a mixture of boron and silicon in the wiring pattern and alloying at least a surface layer of the wiring pattern to form an alloy layer containing aluminum, boron and silicon.

Abstract: Annealing a titanium-rich carbide film deposited on silicon produces, in a single processing step, both a stable titanium silicide contact and a titanium carbide diffusion barrier between the silicide and a subsequently formed overlying layer of aluminum. Reliable low-resistance contacts to VLSI devices are thereby provided in a cost-effective fabrication sequence.Other metallization systems, comprising a silicide and a diffusion barrier to aluminum formed in a single processing step, are also described.

Abstract: An electromechanical transducer is provided, and the process for making it, which utilizes a piezoresistive element or gage which is crystallinally the same as the base or substrate upon which it is supported. The gage of the invention is a force gage, and is derived from its substrate by etching in a series of steps which, ultimately, provide a gage with substantially reduced strain energy requirements, because the volume of the gage may be as small as 33.times.10.sup.10 cubic centimeters of stressed material. In its most preferred form, the element or gage is etched free of its substrate to provide, in effect, a "floating gage. " This is achieved by defining the gage in its substrate or in material rigidly bonded to its substrate, etching away immediately adjacent material, and leaving the gage free in space, while supported at each end on the substrate.

Abstract: A semiconductor device comprising at least one bipolar transistor and at least one MIS FET integrated in a single semiconductor substrate, has an electrode for each region of the bipolar transistor and the MIS FET. Each electrode has the same conductivity type as the corresponding region and is connected to ohmic contact with the surface of the corresponding region.

Abstract: A method of manufacturing solid electrolyte chip capacitors. Each capacitor comprises a substantially rectangular capacitor element having a cathode layer surrounding it, an anode conductor rod protruding therefrom and a pair of electrode terminals disposed on the bottom face thereof. A metal strip, such as the material of electrode terminals, is punched and pressed to form pairs of L-shaped terminals with horizontal legs connected to the remainder of the strip, which face toward and spaced from each other by a distance corresponding to the full length of the capacitor element, each of the vertical legs has a pair of facing side wings separated by a distance corresponding to the width of the capacitor element. The capacitor element is inserted in each enclosure defined by the vertical legs and their wings and positioned precisely, and then encapsulated with synthetic resin. The resultant products are cut off from the strip.

Abstract: Extremely high-purity and defect-free layers of III-V semiconductor materials are produced by a specific MBE process. This process as applied to GaAs includes protecting the deposition substrate with a passivating surface, removing this surface in situ, treating the bared substrate heated to a temperature below its incongruent melting point with an arsenic-containing gas, and initiating the MBE growth in an environment containing an excess of arsenic over gallium.

Abstract: A high performance lateral transistor may be fabricated by first providing a monocrystalline semiconductor body having a principal surface and where the desired transistor is a PNP transistor, a buried N+ region with an N+ reach-through connecting the buried region to said principal surface. The collector region of the transistor is formed into the surface by blanket diffusing P type impurities into the desired region. An insulating layer is formed upon the top surface of the semiconductor body. An opening is made in the insulating layer where the groove or channel-emitter contact is desired. An etching of a substantially vertical walled groove into the monocrystalline semiconductor body using the patterned insulating layer as the etching mask. An N base diffusion is carried out to produce as N region around the periphery of the opening in the body. Oxygen is then ion implanted into the bottom of the groove to form a silicon dioxide region at the bottom of the groove.

Abstract: A method for fabricating an MOS memory array is disclosed, wherein the method includes steps for constructing electrically-programmable and electrically-erasable memory cells (2, 198, 200) in combination with assorted peripheral devices (202, 204, 206) on a semiconductor substrate (8, 71). Tunneling regions (20, 78) are formed in the substrate (8, 71) and thin tunnel dielectrics (22, 84) comprised of silicon dioxide/oxynitride material are grown over the tunneling regions (20, 78) to facilitate transport of charge carriers between the tunneling regions (20, 78) and subsequently-fashioned floating gate structures (14R, 14L, 156) in the memory cells (2, 198, 200). A first layer of doped polycrystalline silicon is then deposited over the substrate and etched to define large polysilicon areas. An oxide layer is grown over the large polysilicon areas in a manner such that out-diffusion of the impurity present in the large polysilicon areas is prevented.

Abstract: A lead frame for a molded semiconductor device package. The lead frame has a pattern of finger leads with convergent free inner ends and dam bars between adjacent finger leads. The dam bars are partially severed from their contiguous finger leads due to cuts on their edges intended to face a body member molded over the finger lead inner ends. The partially severed dam bar edge is preferably positioned to be substantially at the periphery of the molded body member. The resultant molded body member can thus have a finished surface even between the finger leads as molded and dam bar cutting die wear reduced.

Abstract: This invention relates to a method for manufacturing a resin molded semiconductor device.

Abstract: The invention provides a unique sub-micron dimensioned NPN type transistor and method of making the same, wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Spaced apart slots made in the substrate permit the introduction of orientation dependent etching fluid therein to at least substantially etch semi-arrays of active regions of the substrate away from the substrate except for spaced apart supports therealong. Oxidation serves to support the semi-arrays and subsequent steps directly from the substrate or by webs of oxidation along the tops of the semi-arrays connected to the substrate.

Abstract: An apparatus for aligning the leads of an integrated circuit (IC) package with respect to the pads of the printed circuit board to which they will be bonded is presented. An alignment fixture, comprising a coarse alignment pedestal mounted on a fine alignment block, receives the IC package on the alignment fixture and aligns the leads with respect to a reference coordinate system of the alignment fixture. A vacuum chuck is lowered to contact the aligned package, and is then raised to lift the aligned package off the fine alignment block while holding it in the aligned position. An X-Y table positions the printed circuit board under the aligned package. The vacuum chuck lowers the aligned package until the leads contact the pads, and holds it while the leads are bonded to the pads.