Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 ?. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

Abstract: An imaging device capable of executing image processing is provided. A structure is employed in which a photoelectric conversion element, a first transistor, a second transistor, and an inverter circuit are included; one electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor; the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; the one of the source and the drain of the second transistor is electrically connected to an input terminal of the inverter circuit; and data obtained by photoelectric conversion is binarized and output.

Abstract: A display module includes a display panel on which a display area and a non-display area surrounding the display area are defined and a functional layer disposed on the display panel. Here, the functional layer includes a color filter layer including a plurality of color filters and a plurality of first light shielding layers each disposed between the plurality of color filters, a light control layer including a plurality of light control parts overlapping the plurality of color filter layers, respectively, wherein at least one of the plurality of light control parts includes a quantum dot, and a heat conductive layer. The heat conductive layer includes at least one of metal, graphite, and silicon carbide.

Abstract: Disclosed a photosensitive assembly, an imaging module, a smart terminal, and a method and a mould for manufacturing the photosensitive assembly.

Abstract: A semiconductor package includes a die pad and leads extending from the die pad. Each lead has a free end with outer surfaces extending at angles from one another. An electrically conductive plating material covers at least portions of the outer surfaces. A die attached to the die pad is electrically connected to the leads. An insulating layer extends over the leads and the die such that the free ends of the leads are exposed.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure over the dielectric surface. A first protecting structure over the passivation layer. A conductive pad over the dielectric surface. A polymer layer over the first protecting structure and the conductive pad. A conductive bump electrically coupled to the conductive pad through an opening of the polymer layer. A first portion of the first protecting structure is leveled with the conductive pad and a second portion of the first protecting structure is higher than the conductive pad.

Abstract: A semiconductor device is formed by providing a semiconductor die. A laser-assisted bonding (LAB) assembly is disposed over the semiconductor die. The LAB assembly includes an infrared (IR) camera. The IR camera is used to capture an image of the semiconductor die. Image processing is performed on the image to identify corners of the semiconductor die. Regions of interest (ROI) are identified in the image relative to the corners of the semiconductor die. Parameters can be used to control the size and location of the ROI relative to the respective corners. The ROI are monitored for temperature using the IR camera while LAB is performed.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The chip scale package semiconductor device comprises: a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; a carrier comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier; and a molding material partially encapsulating the semiconductor die and the carrier, wherein the first major surface of the carrier extends and is exposed through molding material, and the at least two terminals are exposed through molding material on a second side of the device.

Abstract: CMOS image sensor with LED flickering reduction and low color cross-talk are disclosed. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array that is disposed in a semiconductor substrate. Each pixel includes a plurality of large subpixels (LPDs) and at least one small subpixel (SPD). A plurality of color filters are disposed over individual subpixels. Each individual SPD is laterally adjacent to at least one other SPD.

Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.

Abstract: A metal-dielectric bonding method includes providing a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes: a first semiconductor layer including a complementary metal-oxide-semiconductor device, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, the first metal layer having a metal bonding surface. The metal bonding surface is planarized and a plasma treatment is applied thereto. The second semiconductor structure includes a second semiconductor layer including a pixel wafer, and a second dielectric layer on the second semiconductor layer, the second dielectric layer having a dielectric bonding surface. The dielectric bonding surface is planarized and a plasma treatment is applied thereto. The first and second semiconductor structures are bonded together by bonding the metal bonding surface with the dielectric bonding surface.

Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

Abstract: According to one embodiment, a manufacturing apparatus includes: a storage configured to store a work; a transfer arm configured to transfer the work; a hot bath configured to store a liquid; a mounting table configured to mount the work in the hot bath; and an upper arm configured to apply pressure to the work mounted on the mounting table.

Abstract: According to one embodiment, a semiconductor storage device includes: a plurality of first wiring layers stacked in a first direction; a first memory pillar including a first semiconductor layer extending in the first direction and penetrating the plurality of first wiring layers; a second wiring layer disposed above the first semiconductor layer; a second semiconductor layer including a first part disposed between the first semiconductor layer and the second wiring layer, a second part extending away from the first semiconductor layer, and a third part provided on the second part; a first insulating layer disposed between the first part and the second wiring layer and between the second part and the second wiring layer; and a second insulating layer provided on the first insulating layer and in contact with at least a portion of the second part.

Abstract: A pixel-array substrate includes a floating diffusion region and a first photodiode formed in a semiconductor substrate. A top surface of the semiconductor substrate defines a trench 1A and a trench 1B each (i) extending into the semiconductor substrate away from a planar region of the top surface between the trench 1A and the trench 1B and (ii) having a respective distal end, with respect to the floating diffusion region, located between the floating diffusion region and the first photodiode. In a horizontal plane parallel to the top surface and along an inter-trench direction between the trench 1A and the trench 1B, a first spatial separation between the trench 1A and the trench 1B increases with increasing distance from the floating diffusion region.

Abstract: The present disclosure provides a chip packaging device, a chip packaging method, and a package chip, and is related to a technical field of chip packaging. The chip packaging device includes conductive sheets, a vacuum suction movable assembly defining a variable suction surface, and a heating assembly. The variable suction surface sucks the plurality of conductive sheets. A first end of each of the conductive sheets is disposed above a corresponding bonding pads. A second end of each of the conductive sheets is disposed above a corresponding welding pin, so that when the variable suction surface is pressed down, the first end of each of the conductive sheets is pressed onto the corresponding bonding pad, and the second end of each of the conductive sheets is pressed onto the corresponding welding pin. The heating assembly heats solders on the bonding pads and the welding pins.

Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.

Abstract: A semiconductor device package includes a die, a molding layer, a heat spreader lid, and a warpage control adhesive layer. The molding layer surrounds the die. The molding layer has a first edge and a second edge at least partially defining a corner of the molding layer. The heat spreader lid covers the molding layer and the die. The warpage control adhesive layer is between the heat spreader lid and the molding layer. The warpage control adhesive layer is at the corner of the molding layer and has a bar shape in a top view, and the warpage control adhesive layer extends from the first edge toward the second edge of the molding layer.

Abstract: It is an object to enable a non-destructive inspection of reliability of a bonding part and enabling an accurate inspection. A wedge tool includes: a groove which is formed along a direction of an ultrasonic vibration in a tip portion and in which a bonding wire is disposed in a wedge bonding; a first planar surface and a second planar surface disposed on both sides of the groove; and at least one convex portion formed away from the groove in at least one of the first planar surface and the second planar surface, wherein the bonding wire comes in contact with the convex portion by a deformation of the bonding wire in a bonding part of the bonding wire and a bonded object bonded to each other by a wedge bonding.

Abstract: Disclosed is a method for testing a semiconductor element. The method comprises forming at least one redistribution layer on a chip, utilizing the at least one redistribution layer to test an array of semiconductor elements on the chip, and removing the at least one redistribution layer from the chip, wherein the length of each semiconductor element is between 2-150 ?m and the width of each semiconductor element is between 2-150 ?m.