Abstract: A semiconductor device includes a base plate, a case, and a collar. The base plate includes a metal or an alloy. The base plate has a first bolt hole. The case includes a resin. The case has a first main surface and a second main surface. The second main surface is in contact with the base plate. The case has a through-hole. The collar includes a metal or an alloy. The collar is located within the through-hole. The collar has a first end and a second end. The first end is located on a side where the first main surface is located. The second end is located on a side where the second main surface is located. The collar has a second bolt hole. The first end has a flange. Alternatively, the collar has an outer circumferential surface. The outer circumferential surface has a straight knurling.

Abstract: A chip bonding apparatus and a securing assembly therefor are disclosed. The securing assembly includes a securing bracket, a sliding bracket, and a slide. A first open slot is arranged in the securing bracket, wherein the sliding bracket is slidably mounted on the first open slot, a snap-fitting portion is arranged on a side portion of the sliding bracket, and at least one catch slot that is engageable with the snap-fitting portion to secure the sliding bracket is arranged in the securing bracket. A second open slot is arranged in the sliding bracket, wherein a slideway is arranged in each of two side walls of the second open slot, and the slide is inserted into the slideway and hence mounted in the second open slot.

Abstract: An image sensor includes a substrate having a first surface and a second surface, which are opposite to each other, the substrate including a unit pixel region including a device isolation pattern adjacent to the first surface and a photoelectric conversion region adjacent to the second surface, a pixel isolation pattern provided in the substrate to define the unit pixel regions, an impurity region in the unit pixel region and being adjacent to a side surface of the device isolation pattern, a gate electrode provided on the first surface, and an auxiliary isolation pattern provided between a first side surface of the gate electrode and the impurity region, when the image sensor is viewed in a plan view. A bottom surface of the auxiliary isolation pattern may be located at a level different from a bottom surface of the device isolation pattern.

Abstract: An image sensor includes pixel regions separated by an isolation region and receiving incident light, color filters respectively disposed on a surface of the semiconductor substrate corresponding to the pixel regions, a cover insulating layer disposed on the surface of the semiconductor substrate and covering the color filters, first transparent electrodes disposed on the cover insulating layer and spaced apart to respectively overlap the color filters, an isolation pattern disposed on the cover insulating layer between the first transparent electrodes and having a trench spaced apart from the first transparent electrodes, a drain electrode disposed in the trench of the isolation pattern, and an organic photoelectric layer and a second transparent electrode sequentially disposed on the first transparent electrodes and the isolation pattern.

Abstract: In an embodiment a component assembly includes a plurality of components, a carrier, wherein the components are secured on the carrier by a connecting layer, wherein, for each component, the connecting layer forms at least one supporting structure at which the connecting layer is adjacent to the component, and a sacrificial layer arranged regionally between the components and the connecting layer, wherein one portion of the components is assigned to a first group, wherein a further portion of the components is assigned to a second group, and wherein the components of the first group are different than the components of the second group in respect of a coverage with the sacrificial layer.

Abstract: A method for forming a semiconductor structure and a semiconductor structure are provided. The method includes following operations. A semiconductor substrate is provided. The semiconductor substrate includes an array region and a peripheral region, a plurality of conductive layers are arranged in array region and separated from each other. A support layer covering the semiconductor substrate is formed. An interconnect layer is arranged in support layer located on the array region and extends to peripheral region. The interconnect layer is electrically connected to a respective one of the conductive layers and transmits an electrical signal of the respective one of the conductive layers to the peripheral region. The support layer is patterned to form a plurality of support structures located on the peripheral region and separated from each other and an interconnect structure located on the array region and peripheral region. The interconnect layer is located in the interconnect structure.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a first side and a second side opposing the first side. The substrate has one or more sidewalls defining a trench extending along opposing sides of a pixel region having a first width. An isolation structure including one or more dielectric materials is disposed within the trench. The isolation structure has a second width. An image sensing element and a focal region are disposed within the pixel region. The focal region is configured to receive incident radiation along the second side of the substrate. A ratio of the second width to the first width is in a range of between approximately 0.1 and approximately 0.2, so that the focal region is completely confined between interior sidewall of the isolation structure facing the image sensing element.

Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

Abstract: A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to a position above the wire bond; (c) moving the wire bonding tool to contact the length of wire, at a position along the length of wire, to partially sever the length of wire at the position along the length of wire; and (d) separating the length of wire from a wire supply at the position along the length of wire, thereby providing a wire interconnect structure bonded to the bonding location.

Abstract: A driving backplane includes: a base; a first conductive layer disposed on the base, the first conductive layer including at least one first signal line; a first insulating layer disposed on a side of the first conductive layer away from the base; a second conductive layer disposed on a side of the first insulating layer away from the first conductive layer, the second conductive layer including at least one second signal line. Each first signal line and a second signal line constitute a signal line pair. In the signal line pair, extending directions of the first signal line and the second signal line are the same, an orthogonal projection of the first signal line on the base and an orthogonal projection of the second signal line on the base have a first overlapping region, and the second signal line is coupled to the first signal line.

Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

Abstract: A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure.

Abstract: Provided is an imaging element that includes a semiconductor substrate, a first photoelectric converter, a through electrode, a first dielectric film, and a second dielectric film. The semiconductor substrate has one surface and another surface that are opposed to each other. The semiconductor substrate has a through hole penetrating between the one surface and the other surface. The first photoelectric converter is provided above the one surface of the semiconductor substrate. The through electrode is electrically coupled to the first photoelectric converter and penetrates the semiconductor substrate inside the through hole. The first dielectric film is provided on the one surface of the semiconductor substrate and has a first film thickness. The second dielectric film is provided on a side surface of the through hole and has a second film thickness. The second film thickness is less than the first film thickness.

Abstract: Electronic assembly methods and structures are described. In an embodiment, an electronic assembly method includes bringing together an electronic component and a routing substrate, and directing a large area photonic soldering light pulse toward the electronic component to bond the electronic component to the routing substrate.

Abstract: A transfer device of micro-elements and manufacturing method thereof are provided in the present disclosure. The transfer device of micro-elements may comprise a vacuum chamber, a plurality of movable mass blocks and a plurality of electrode assemblies. The vacuum chamber may define a vacuum space and a plurality of through holes. The plurality of through holes can communicate the vacuum space with outside. The plurality of through holes can be configured to suck the micro-elements. The plurality of movable mass blocks may be arranged in the vacuum chamber. Each movable mass block may be arranged corresponding to a through hole. The plurality of electrode assemblies may be fixed in the vacuum chamber. Each electrode assembly can be arranged corresponding to a through hole.

Abstract: The present disclosure relates to a double-sided integrated circuit (IC) module, which includes an exposed semiconductor die on a bottom side. A double-sided IC module includes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side of the module substrate is removed, exposing a semiconductor die surface of at least one of the electronic components.

Abstract: An image sensor includes a substrate having a pixel area in which a plurality of active areas is defined. A first transistor includes a first gate electrode including a buried gate portion. The buried gate portion is buried in the substrate in a first active area selected from the plurality of active areas. A second transistor includes a second gate electrode overlapping the buried gate portion on the first active area in a vertical direction.

Abstract: A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.

Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.

Abstract: A bonding tool and a bonding method are provided. The method includes attaching a semiconductor die to a bonding tool having a first surface, wherein the bonding tool comprises a bending member movably arranged in a trench of the bonding tool, and the bending member protrudes from the first surface and bends the semiconductor die; moving the semiconductor die toward a semiconductor wafer to cause a retraction of the bending member and a partial bonding at a portion of the semiconductor die and the semiconductor wafer; and causing a full bonding between the semiconductor die and the semiconductor wafer subsequent to the partial bonding.