Abstract: A semiconductor apparatus includes a semiconductor layer that includes a photoelectric conversion unit disposed between a front surface and a back surface and a transistor disposed at the front surface, and a dielectric film in contact with the back surface, wherein the semiconductor layer includes a region extending 100 nm from the back surface, the region having boron concentrations whose maximum value is more than 1×1020 [atoms/cm3].

Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed within a substrate. The substrate has a front-side surface and a back-side surface. An absorption enhancement structure is disposed along the back-side surface of the substrate and overlies the photodetector. The absorption enhancement structure includes a plurality of protrusions that extend outwardly from the back-side surface of the substrate. Each protrusion comprises opposing curved sidewalls.

Abstract: A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.

Abstract: A semiconductor module includes: a case; a semiconductor chip provided inside the case; a seal material injected to inside of the case and sealing the semiconductor chip; and a lid provided inside the case and contacting an upper surface of the seal material, wherein a tapered portion is provided at an end portion of the lid on an upper surface side, a gap is provided between a side surface of the end portion of the lid and an inner side surface of the case, and the seal material crawls up to the tapered portion through the gap.

Abstract: A packaged radio frequency transistor amplifier includes a package housing, an RF transistor amplifier die that is mounted within the package housing, a first capacitor die that is mounted within the package housing, an input leadframe that extends through the package housing to electrically connect to a gate terminal of the RF transistor amplifier die, and an output leadframe that extends through the package housing to electrically connect to a drain terminal of the RF transistor amplifier die. The output leadframe includes an output pad region, an output lead that extends outside of the package housing, and a first arm that extends from one of the output pad region and the output lead to be adjacent the first capacitor die.

Abstract: A curved FPA comprises an array of detectors, with mesas etched between the detectors such that they are electrically and physically isolated from each other. Metallization deposited at the bottom of the mesas reconnects the detectors electrically and thereby provides a common ground between them. Strain induced by bending the FPA into a curved shape is across the metallization and any backfill epoxy, rather than across the detectors. Indium bumps are evaporated onto respective detectors for connection to a readout integrated circuit (ROIC). An ROIC coupled to the detectors is preferably thinned, and the backside of the ROIC may also include mesas such that the ROIC is reticulated.

Abstract: There is provided a solid-state imaging device that includes a photoelectric conversion unit, a transfer gate, a floating diffusion unit, and a transistor. The photoelectric conversion unit produces a charge according to incident light. The transfer gate has a columnar shape having an opening that is continuous in a vertical direction, and transfers the charge from the photoelectric conversion unit. The floating diffusion unit is formed extending to a region surrounded by the opening of the transfer gate, and converts the transferred charge into a voltage signal. The transistor is electrically connected to the floating diffusion unit via a diffusion layer.

Abstract: A method of manufacturing a semiconductor device including: arranging a first and a second gate strip separating in a first distance, wherein each of the first and the second gate strip is a gate terminal of a transistor; depositing a first contact via on the first gate strip; forming a first conductive strip on the first contact via, wherein the first conductive strip and the first gate strip are crisscrossed from top view; arranging a second and a third conductive strip, above the first conductive strip, separating in a second distance, wherein each of the second and the third conductive strip is free from connecting to the first conductive strip, the first and the second conductive strip are crisscrossed from top view. The first distance is twice as the second distance. A length of the first conductive strip is smaller than two and a half times as the first distance.

Abstract: A combination structure includes an in-plane pattern of unit cells, wherein the each unit cell includes nanostructures each having a dimension that is smaller than a near-infrared wavelength and a light-absorbing layer adjacent to the nanostructures and including a near-infrared absorbing material configured to absorb light in at least a portion of a near-infrared wavelength spectrum. The nanostructures are define a nanostructure array in the unit cells, and a wavelength width at 50% transmittance of a transmission spectrum in the near-infrared wavelength spectrum of the combination structure is wider than a wavelength width at 50% transmittance of a transmission spectrum in the near-infrared wavelength spectrum of the nanostructure array.

Abstract: Wafer-level packaging structure is provided. First chips are bonded to the device wafer. A first encapsulation layer is formed on the device wafer, covering the first chips. The first chip includes: a chip front surface with a formed first pad, facing the device wafer; and a chip back surface opposite to the chip front surface. A first opening is formed in the first encapsulation layer to expose at least one first chip having an exposed chip back surface for receiving a loading signal. A metal layer structure is formed covering the at least one first chip, a bottom and sidewalls of the first opening, and the first encapsulation layer, followed by an alloying treatment on the chip back surface and the metal layer structure to form a back metal layer on the chip back surface.

Abstract: The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplane of a display device. The LEDs may be ?LEDs. The pulsed photon source is employed to irradiate the LEDs with scanning photon pulses. The EM radiation is absorbed by either the surfaces, bulk, substrate, the electrical contacts of the LED, and/or electrical contacts of the backplane to generate thermal energy that induces the bonding between the electrical contacts of the LEDs' electrical contacts and backplane's electrical contacts. The temporal and spatial profiles of the photon pulses, as well as a pulsing frequency and a scanning frequency of the photon source, are selected to control for adverse thermal effects.

Abstract: A solid-state image sensor including: a first impurity region of a first conductivity type; a plurality of second impurity regions of a second conductivity type disposed in the first impurity region and arranged in a first direction; and a light shielding layer that overlaps the first impurity region and does not overlap the second impurity regions in a plan view, wherein the first impurity region has a first portion between adjacent ones of the second impurity regions, the light shielding layer has a second portion that overlaps the first portion in a plan view, and a length of the second portion in the first direction is smaller than a length of the first portion in the first direction.

Abstract: A semiconductor device includes gate electrodes stacked to be spaced apart from each other on a substrate in a first direction, extending in a second direction, and including pad regions bent in a third direction, sacrificial insulating layers extending from the gate electrodes to be stacked alternately with the interlayer insulating layers, separation regions penetrating through the gate electrodes, extending in the second direction, and spaced apart from each other to be parallel to each other, and a through-wiring region spaced apart from the separation regions to overlap the pad regions between the separation regions adjacent to each other and including contact plugs penetrating through the pad regions. The through-wiring region includes slit regions, and each of the slit regions is disposed to penetrate through the sacrificial insulating layers on one side of a respective pad region.

Abstract: The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplane of a display device. The LEDs may be ?LEDs. The pulsed photon source is employed to irradiate the LEDs with scanning photon pulses. The EM radiation is absorbed by either the surfaces, bulk, substrate, the electrical contacts of the LED, and/or electrical contacts of the backplane to generate thermal energy that induces the bonding between the electrical contacts of the LEDs' electrical contacts and backplane's electrical contacts. The temporal and spatial profiles of the photon pulses, as well as a pulsing frequency and a scanning frequency of the photon source, are selected to control for adverse thermal effects.

Abstract: A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact.

Abstract: A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T1 at a first end of the opening, and a thickness T2 at a second end of the opening, and R1 is a ratio of T1 to T2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T3 at the first end of the opening, a thickness T4 at the second end of the opening, R2 is a ratio of T3 to T4, and R1 is greater than R2.

Abstract: An energy harvesting imaging sensor includes an array of pixel structures each formed from a semiconductor having a photodiode overlying a photovoltaic diode. The photodiode and photovoltaic diode are implemented as a vertically stacked P+/NWELL/PSUB junction. This structure enables simultaneous imaging and energy harvesting by generating charge in the photodiode that is indicative of light impinging on the photodiode and simultaneously generating charge from the light in the photovoltaic diode located underneath the photodiode.

Abstract: A semiconductor module includes: a case; a semiconductor chip provided inside the case; a seal material injected to inside of the case and sealing the semiconductor chip; and a lid provided inside the case and contacting an upper surface of the seal material, wherein a tapered portion is provided at an end portion of the lid on an upper surface side, a gap is provided between a side surface of the end portion of the lid and an inner side surface of the case, and the seal material crawls up to the tapered portion through the gap.

Abstract: Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) an indication positioned in a designated area of the first surface. The indication includes a code presenting information for operating the semiconductor die. The code is configured to be read by an indication scanner coupled to a controller.

Abstract: A photoelectric conversion device including a plurality of substrates in a stacked state, the plurality of substrates including a first substrate and a second substrate electrically connected to each other, the photoelectric conversion device comprising: a memory cell unit including row-selection lines that are to be driven upon selection of a row of a memory cell array and column-selection lines that are to be driven upon selection of a column of the memory cell array; and a memory peripheral circuit unit that includes row-selection line connection portions and column-selection line connection portions so as to drive the row-selection lines and to drive the column-selection lines, wherein a first portion that is at least a part of the memory peripheral circuit unit is formed on the first substrate and the memory cell unit is formed on the second substrate.