Patents Examined by David A. Zarneke
  • Patent number: 10658289
    Abstract: Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two-adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: May 19, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yunjung Choi, Kivin Im, Dongbok Lee, Inseak Hwang
  • Patent number: 10643936
    Abstract: A package substrate including a fine redistribution circuitry, a first redistribution circuitry disposed on the fine redistribution circuitry and a core disposed on the first redistribution circuitry opposite to the fine redistribution circuitry. The fine redistribution circuitry includes a fine conductive pattern. The first redistribution circuitry includes a first conductive pattern electrically connected to the fine conductive pattern. A thickness of the fine redistribution circuitry is less than a thickness of the first redistribution circuitry and a dimension of the fine conductive pattern is less than a dimension of the first conductive pattern. The core is electrically connected to the first conductive pattern. The Young's modulus of the core is greater than the Young's modulus of the first redistribution circuitry. A package structure is also provided.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: May 5, 2020
    Inventor: Dyi-Chung Hu
  • Patent number: 10636858
    Abstract: A display device includes a base layer having a first surface and a second surface, a display region arranged on the first surface of the base layer, a drive circuit region arranged on the outer side of the display region, and a wiring region between the display region and the drive circuit region. The wiring region includes a plurality of wirings having a plurality of connected polygonal shaped conductive patterns in which the inner portions thereof are removed, the base layer includes a plurality of through-holes penetrating from the first surface to the second surface in the wiring region, and the plurality of through-holes are arranged on the inner portion of the conductive pattern.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: April 28, 2020
    Assignee: Japan Display Inc.
    Inventor: Takuma Nishinohara
  • Patent number: 10636737
    Abstract: A semiconductor device includes a contact via and a metal interconnect on the contact via. The metal interconnect has a portion extending in a lengthwise direction that is wrapped around and in contact with a sidewall of the contact via. Along a widthwise direction, the metal interconnect does not contact the sidewall of the contact via.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: April 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Junjing Bao, Jie Deng, John Zhu, Giridhar Nallapati
  • Patent number: 10629537
    Abstract: An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 10629457
    Abstract: Provided is a method for manufacturing a semiconductor device through which improvement of production efficiency can be achieved. In the method of manufacturing the semiconductor device (1), a sealing material (7) is attached to seal a semiconductor element (3), a release film (F) is provided in a mold facing the semiconductor element (3), and the sealing material (7) is cured by an upper mold (22) and a lower mold (24). A metal layer (9) that shields electromagnetic waves is previously provided on a side of the release film (F) coming in contact with the sealing material (7). In the curing of the sealing material (7), the metal layer (9) is transferred to the sealing material (7).
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: April 21, 2020
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Takashi Kawamori, Naoya Suzuki
  • Patent number: 10607848
    Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: March 31, 2020
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yuan-Chieh Chiu, Shih-Ping Hong, Kuang-Chao Chen, Yen-Ju Chen
  • Patent number: 10593609
    Abstract: A semiconductor device includes: at least one power semiconductor element; a sealing resin disposed so as to seal the power semiconductor element; and a plurality of electrical terminals each electrically connected to the power semiconductor element and each including a protrusion protruding from a surface of the sealing resin. The protrusion includes a first part that is provided on a side of the sealing resin in a protrusion direction of the protrusion and of which a cross-section intersecting the protrusion direction has one of a circular shape and an oval shape.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: March 17, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuji Nishibe, Yasuyuki Kageyama, Yasuyoshi Saito, Shinichi Miura, Yasuhide Yagyu
  • Patent number: 10593638
    Abstract: Methods and apparatus are described for enabling copper-to-copper (Cu—Cu) bonding at reduced temperatures (e.g., at most 200° C.) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure generally includes a semiconductor layer, an adhesion layer disposed above the semiconductor layer, an anodic metal layer disposed above the adhesion layer, and a cathodic metal layer disposed above the anodic metal layer. An oxidation potential of the anodic metal layer may be greater than an oxidation potential of the cathodic metal layer. Such a semiconductor structure may be utilized in fabricating IC packages implementing 2.5D or 3D integration.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: March 17, 2020
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam, Henley Liu
  • Patent number: 10586764
    Abstract: Semiconductor packages with programmable routing pathways are disclosed. The semiconductor package may have a source trace that may be electrically coupled to two or more different electrical pathways, where any of the electrical pathways may be activated to provide an electrical connection between the source trace and one or more destination nodes. Each of the electrical pathways may have a corresponding metal well with a correspond airgap overlying the metal well, as well as corresponding heating elements. If a particular heating element is energized, the heating element may melt metal in a corresponding metal well and the molten metal may migrate by capillary action into the overlying airgap to complete an electrical connection between the source trace and a destination node.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Russell S. Aoki, Dimitrios Ziakas
  • Patent number: 10580726
    Abstract: A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Ho Chun, Seong-Min Son, Hyung-Jun Jeon, Kwang-Jin Moon, Jin-Ho An, Ho-Jin Lee, Atsushi Fujisaki
  • Patent number: 10580755
    Abstract: A fan-out wafer level multilayer wiring package structure, wherein the package structure comprises a plurality of semiconductor chips, a multilayer interposer, a vertical interconnection interposer, molding materials and a redistribution layer; the back surface of the semiconductor chip is bonded to the back surface of the multilayer wiring interposer with the bonding material, and is placed on the same horizontal plane as the vertical interconnection interposer and packaged as a whole with the molding material, the redistribution layer is provided on the surface of the structure; the semiconductor chip, the multilayer interposer, the conductive material of the vertical interconnection interproser and the solder ball are connected by the conductive metal layer of the redistribution layer to achieve the signal interconnection between the semiconductor chip and the multilayer interposer and the I/O signal transfer of the semiconductor chip.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 3, 2020
    Assignee: The 58th Research Institute of China Electronics Technology Group Corporation
    Inventors: Yong Ji, Rongzhen Zhang, Chongchong Mao
  • Patent number: 10566313
    Abstract: An integrated circuit (IC) chip carrier includes an IC chip electrically connected to an IC chip carrier by a plurality of chip-carrier contacts, a cover thermally connected the IC chip upper surface, and an in-plane thermal conductance (ITC) layer upon the IC chip carrier between the IC chip carrier and the IC chip. The ITC layer includes an extension tab connected to a vertical side surface of the cover. Heat is transferred vertically from the IC chip to the cover. Heat is also transferred vertically from the IC chip to the ITC layer. Heat is also transferred within the ITC layer through the ITC layer basal plane(s). The ITC layer basal plane(s) are positioned horizontally where the ITC layer is between the IC chip and the IC chip carrier. The ITC layer basal planes are positioned vertically where the extension tab contacts the vertical side surface of the cover.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Shidong Li, Kamal K. Sikka
  • Patent number: 10546760
    Abstract: A method of manufacturing a semiconductor device that includes a resin package sealing a semiconductor element and a pair of metal plates interposing the semiconductor element therebetween, in which each of the pair of metal plates is exposed at corresponding one of both surfaces of the resin package is disclosed. The method may include preparing an assembly in which the semiconductor element is connected to the pair of metal plates; setting the assembly in a cavity of a mold, wherein one metal plate is in contact with a bottom surface of the cavity and a space is provided above the other metal plate; forming the resin package by injecting a molten resin into the cavity so as to cover an upper side of the other metal plate, stopping the injecting of the molten resin with a part of the space on an upper side of the cavity unfilled.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: January 28, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takuya Kadoguchi, Yuuji Hanaki, Atsuko Yamanaka, Shou Funano, Satoshi Takahagi, Shingo Iwasaki
  • Patent number: 10546774
    Abstract: An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a ? line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a ? line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an ? line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a ??? jog; a ??? jog; and ??? jog; a ??? jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
  • Patent number: 10541219
    Abstract: A base plate having concave curved portions (rearward-convex parts) curved in a rearward direction to be convex and have a predetermined curvature, is fixed to a surface of a cooling fin while being in contact with the surface of the cooling fin at vertices of the rearward-convex parts. A stacked substrate is bonded on a front surface of the base plate, at an area opposing the rearward-convex part. A spacer is provided on a rear surface of the base plate, at a position closer than an edge of a solder layer to a perimeter of the base plate. The spacer is sandwiched between the base plate and the cooling fin when a screw for fixing the base plate to the cooling fin is tightened and the spacer has a function of suppressing deformation of the base plate.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: January 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshinori Uezato
  • Patent number: 10535535
    Abstract: A semiconductor product such as an integrated circuit includes a laminar plastic substrate having first and second opposed surfaces and through holes extending through the substrate, electrically and/or thermally conductive material balls inserted in the through holes at the first surface of the substrate, and one or more semiconductor chips mounted at the first surface of the substrate, the semiconductor chip(s) electrically and/or thermally coupled with electrically and/or thermally conductive material balls inserted in the through holes.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: January 14, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Fabio Marchisi
  • Patent number: 10529788
    Abstract: A pattern structure for a display device includes a substrate, a protrusion pattern on the substrate, a first conductive pattern covering an upper surface of the protrusion pattern, an interlayer insulating layer on the first conductive pattern and including a contact hole, and a second conductive pattern on the interlayer insulating layer and connected to the first conductive pattern. The contact hole overlaps the protrusion pattern and the first conductive pattern.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Se Wan Son, Jung Hwa Kim, Jin Sung An, Wang Woo Lee, Ji Seon Lee, Moo Soon Ko
  • Patent number: 10510722
    Abstract: A semiconductor device includes a first electronic component, a second electronic component and a plurality of interconnection structures. The first electronic component has a first surface. The second electronic component is over the first electronic component, and the second electronic component has a second surface facing the first surface of the first electronic component. The interconnection structures are between and electrically connected to the first electronic component and the second electronic component, wherein each of the interconnection structures has a length along a first direction substantially parallel to the first surface and the second surface, a width along a second direction substantially parallel to the first surface and the second surface and substantially perpendicular to the first direction, and the length is larger than the width of at least one of the interconnection structures.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Weiming Chris Chen, Tu-Hao Yu, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
  • Patent number: 10510701
    Abstract: A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chen-Hua Yu, Sen-Bor Jan