Abstract: A package for power electronics includes a power substrate, a number of power semiconductor die, and a Kelvin connection contact. Each one of the power semiconductor die are on the power substrate and include a first power switching pad, a second power switching pad, a control pad, a semiconductor structure, and a Kelvin connection pad. The semiconductor structure is between the first power switching pad, the second power switching pad, and the control pad, and is configured such that a resistance of a power switching path between the first power switching pad and the second power switching pad is based on a control signal provided at the control pad. The Kelvin connection pad is coupled to the power switching path. The Kelvin connection contact is coupled to the Kelvin connection pad of each one of the power semiconductor die via a Kelvin conductive trace on the power substrate.

Abstract: Disclosed are image sensors and methods of fabricating the same. The image sensor includes a semiconductor substrate including a pixel zone and a pad zone and having a first surface and a second surface opposing each other, a first pad separation pattern on the pad zone and extending from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate, a second pad separation pattern extending from the second surface toward the first surface of the semiconductor substrate on the pad zone the second pad and in contact with the first pad separation pattern, and a pixel separation pattern on the pixel zone and extending from the second surface of the semiconductor substrate toward the first surface of the semiconductor substrate.

Abstract: Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die surrounded by a first molding compound layer. A redistribution layer (RDL) structure is formed on a non-active surface of the semiconductor die and the first molding compound layer. A second molding compound layer is formed on the RDL structure. An insulating capping layer covers the second molding compound layer. An antenna is electrically coupled to the semiconductor die and includes a first antenna element formed in the RDL structure and a second antenna element formed between the second molding compound layer and the insulating capping layer.

Abstract: The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplane of a display device. The LEDs may be ?LEDs. The pulsed photon source is employed to irradiate the LEDs with scanning photon pulses. The EM radiation is absorbed by either the surfaces, bulk, substrate, the electrical contacts of the LED, and/or electrical contacts of the backplane to generate thermal energy that induces the bonding between the electrical contacts of the LEDs' electrical contacts and backplane's electrical contacts. The temporal and spatial profiles of the photon pulses, as well as a pulsing frequency and a scanning frequency of the photon source, are selected to control for adverse thermal effects.

Abstract: An apparatus for aligning dipoles is provided. The apparatus includes: an electric field forming unit including a stage and a probe unit, the probe unit being configured to form an electric field on the stage; an inkjet printing device including an inkjet head, the inkjet head being configured to spray ink including a solvent and dipoles dispersed in the solvent onto the stage; a light irradiation device configured to irradiate light onto the stage; and a temperature control device including a temperature control unit, the temperature control unit being configured to control a temperature of the solvent sprayed on the stage.

Abstract: A display apparatus includes a buffer layer on a substrate, a first hole penetrating the buffer layer and exposing a portion of the substrate, a display layer with display elements and bypass lines on the buffer layer, a second hole penetrating the display layer and connected to the first hole, and an encapsulation member covering the display elements and the bypass lines. The bypass lines are configured to extend along a portion of a perimeter of the second hole and are disposed between the second hole and the display elements. At least a portion of an upper surface of the buffer layer is exposed by the second hole.

Abstract: A method of forming an image detector from an optical detector having a first side connected to a substrate and a second side opposite the first side. The method includes: receiving the detector; electrically coupling the second side of the detector to a read out integrated circuit (ROIC); securing the detector to the ROIC with an adhesive, wherein the adhesive surrounds the detector and at least a portion of the substrate. The method also includes chemically removing at least some of the substrate to expose an exposed portion of the first side of the detector. Such removal results in the formation of an adhesive fence from the adhesive that has a fence upper surface that is above the first side on which an optical element is mounted such that an air gap exists between the first side of the detector and the optical element.

Abstract: A 3D semiconductor memory device includes a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure comprising stacked electrodes, and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure includes a dummy interconnection structure under the second substrate. The dummy interconnection structure includes stacked interconnection lines, and a via connecting a top surface of an uppermost one of the interconnection lines to a bottom surface of the second substrate.

Abstract: Semiconductor device fabrication method is provided. The method includes providing a substrate; forming a first semiconductor layer on the substrate; forming a stack of semiconductor layer structures on the first semiconductor layer, each of the semiconductor layer structures comprising a second semiconductor layer and a third semiconductor layer on the second semiconductor layer, the second and third semiconductor layers having at least a common compound element, and the third semiconductor layer and the first semiconductor layer having a same semiconductor compound; performing an etching process to form a fin structure; performing a selective etching process on the second semiconductor layer to form a first air gap between the first semiconductor layer and the third semiconductor layer and a second air gap between each of adjacent third semiconductor layers in the stack of one or more semiconductor layer structures; and filling the first and second air gaps with an insulator layer.

Abstract: A semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; and a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells includes at least one second transistor, where the control circuits control access to the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least a portion of the array of memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.

Abstract: A bonding apparatus includes a stage on which a substrate is seated, a gantry installed above the stage, a bonding unit configured to bond a chip to the substrate while moving along the gantry, and a control part moving the bonding unit to align the bonding unit with a bonding position on the substrate, controlling the bonding unit to allow the bonding unit to bond the chip at the bonding position, determining a movement distance of the bonding unit based on a weighted sum of a number of continuous operations and an idle time of the bonding unit.

Abstract: An image sensor includes a detection region, a first transistor region, and a second transistor region. The detection region including a first demodulation node and a second demodulation node generates a hole current in a substrate, and captures photocharges that are generated by incident light and move by the hole current. The first pixel transistor region including a plurality of transistors is disposed at one side of the detection region, and processes photocharges captured by the first demodulation node. The second pixel transistor region including a plurality of transistors is disposed at other side of the detection region, and processes photocharges captured by the second demodulation node.

Abstract: A method for forming a pixel includes forming, in a semiconductor substrate, a wide trench having an upper depth with respect to a planar top surface of the semiconductor substrate. The method also includes ion-implanting a floating-diffusion region between the planar top surface and a junction depth in the semiconductor substrate. In a cross-sectional plane perpendicular to the planar top surface, the floating-diffusion region has (i) an upper width between the planar top surface and the upper depth, and (ii) between the upper depth and the junction depth, a lower width that exceeds the upper width. Part of the floating-diffusion region is beneath the wide trench and between the upper depth and the junction depth.

Abstract: A method for fabricating a semiconductor die package includes: providing a semiconductor transistor die, the semiconductor transistor die having a first contact pad on a first lower main face and/or a second contact pad on an upper main face; fabricating a frontside electrical conductor onto the second contact pad and a backside electrical conductor onto the first contact pad; and applying an encapsulant covering the semiconductor die and at least a portion of the electrical conductor, wherein the frontside electrical conductor and/or the backside electrical conductor is fabricated by laser-assisted structuring of a metallic structure.

Abstract: An image sensing device includes a pixel array including a plurality of unit pixels consecutively arranged and structured to generate an electrical signal in response to incident light by performing photoelectric conversion of the incident light. The unit pixels are isolated from each other by first device isolation structures. Each of the unit pixels includes a photoelectric conversion element structured to generate photocharges by performing photoelectric conversion of the incident light, a floating diffusion region structured to receive the photocharges, a transfer transistor structured to transfer the photocharges generated by the photoelectric conversion element to the floating diffusion region, and a well tap region structured to apply a bias voltage to a well region. The well tap region is disposed at a center portion of a corresponding unit pixel.

Abstract: The present disclosure is directed to a high throughput clip bonding tool or system which is flexible and easily adapts to different clip bond pitches or sizes. The clip bonding system may be an integrated system with various modules, including a clip singulation module, a feeder module, a transfer module and a clip attach module within a shared footprint. For example, an incoming clip source may be fed to the clip singulation module for clip singulation before the singulated clips are transferred by the feeder and transfer modules to a clip presentation area for clip alignment before pickup. A pickup tool of the clip attach module is configured to facilitate pickup and attachment of clips onto the semiconductor packages to be clip bonded. For example, the pickup head is programmable to facilitate clip bonding process of different applications which may require clips and packages with different sizes.

Abstract: A method for making a micro-electro mechanical (MEMS) device includes forming a MEMS mirror stack on a handle layer, and applying a first bonding layer to the MEMS mirror stack. The method continues with disposing a substrate on the first bonding layer such that the MEMS mirror stack is mechanically anchored to the substrate and so as to seal against ingress of environmental contaminants, removing the handle layer, and applying a second bonding layer to the MEMS mirror stack. A cap layer is disposed on the second bonding layer such that the cap layer is mechanically anchored to the MEMS mirror stack and so as to seal against ingress of environmental contaminants.

Abstract: An image sensing device includes a substrate structured to include a first surface on a first side of the substrate and a second surface on a second side of the substrate opposite to the first side and to further include a first active region and a second active region in a portion of the substrate near the second surface, at least one photoelectric conversion element formed in the substrate, and structured to generate photocharges by performing photoelectric conversion of incident light received through the first surface of the substrate, a floating diffusion region formed near the second surface of the substrate, and structured to receive the photocharges from the photoelectric conversion element and temporarily store the received photocharges, a transistor formed in the first active region, and structured to include a first source/drain region coupled to the floating diffusion region, and a well pickup region formed in the second active region, and structured to apply a bias voltage to the substrate.

Abstract: An optical electronics device includes first, second and third wafers. The first wafer has a semiconductor substrate with a dielectric layer on a side of the semiconductor substrate. The second wafer has a transparent substrate with an anti-reflective coating on a side of the transparent substrate. The first wafer is bonded to the second wafer at a silicon dioxide layer between the semiconductor substrate and the anti-reflective coating. The first and second wafers include a cavity extending from the dielectric layer through the semiconductor substrate and through the silicon dioxide layer to the anti-reflective coating. The third wafer includes micromechanical elements. The third wafer is bonded to the dielectric layer, and the micromechanical elements are contained within the cavity.