Abstract: SOI Transistor Having a Self-aligned Body Contact An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

Abstract: Disclosed is a gate electrode stack structure that uses a refractory metal silicon nitride layer as a diffusion barrier. The gate electrode stack has several layers, including a gate oxide layer over the semiconductor substrate, a polysilicon layer over the gate oxide layer, and the diffusion barrier between the polysilicon layer and a layer of electrically conductive material above. The diffusion barrier, which is preferably composed of a substantially amorphous refractory metal silicon nitride such as tungsten silicon nitride, of does not oxidize when an oxidation process is applied to the gate electrode stack. Moreover, the diffusion barrier substantially prevents diffusion of the electrically conductive material into the polysilicon during heating processes. The refractory metal silicon nitride maintains a bulk resistivity less than 2,000 microhm-cm, thereby preserving satisfactory conductivity in the gate electrode stack.

Abstract: A semiconductor device package comprises a circuit substrate, a semiconductor device chip mounted on the circuit substrate, a plurality of end-face halved through-holes formed on an end-face of the circuit substrate, in the form obtained by halving a through hole along its center axis, and having an inner side surface coated with a conductor film, a plurality of wiring conductors formed on an upper surface of the circuit substrate and connected to the end-face halved through-holes, a plurality of external electrode conductors formed on a lower surface of the circuit substrate and connected to the end-face halved through-holes, and a solder resist provided to partially cover the external electrode conductors for separating an end of the external electrode conductors from the end-face halved through-holes.

Abstract: A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region.

Abstract: A laser imaging system is used to analyze defects on semiconductor wafers that have been detected by patterned wafer defect detecting systems (wafer scanners). The laser imaging system replaces optical microscope review stations now utilized in the semiconductor fab environment to examine detected optical anomalies that may represent wafer defects. In addition to analyzing defects, the laser imaging system can perform a variety of microscopic inspection functions including defect detection and metrology. The laser imaging system uses confocal laser scanning microscopy techniques, and operates under class 1 cleanroom conditions and without exposure of the wafers to operator contamination or airflow.

Abstract: A semiconductor integrated circuit device has a protective structure between a semiconductor chip and a ball grid array, and the protective structure has a thin polyimide film bonded to the surface of the semiconductor chip and a thick stress relaxation layer covering conductive strips connected between pads on the surface and the ball grid array; when thermal stress is exerted on the ball grid array, the thick stress relaxation layer allows said ball grid array to move so as to take up the thermal stress.

Abstract: A method for producing a semiconductor configuration, such as a field plate insulating transistor, is suitable for providing mutual insulation of two complementary wells in a substrate. A first insulation layer, a dopable layer and a sacrificial layer are applied on the substrate. A first region of the sacrificial layer is removed to form an edge through the use of a first mask technique, and a first region of the dopable layer which is thereby bared is doped simultaneously with the substrate located beneath, creating the first well. The second well is produced analogously, with the edge serving as an adjustment mark for a requisite second mask technique. It is not until after the doping that a second insulation layer is applied, which is then structured to form the insulating transistor.

Abstract: In the nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix of the present invention, the memory cell array includes: a semiconductor substrate; a tunnel oxide film formed on the semiconductor substrate; floating gates formed on the tunnel oxide film; first insulating films formed on the floating gates; and control gates formed on the first insulating films, wherein each of the floating gates includes a first polysilicon film and second polysilicon films, the second polysilicon films being formed on both sides of the first polysilicon film, second insulating films are formed on the tunnel oxide film between the first polysilicon films, the second insulating films having a predetermined thickness which is thinner than that of the first polysilicon films, and the second polysilicon films are formed on the second insulating films.

Abstract: In forming a single phase CrN film suitable for a barrier film of the copper wiring, the manufacturing conditions for forming the barrier film are determined in advance. The semiconductor device is manufactured using the predetermined conditions. Single phase CrN film is preferred as a barrier film for preventing diffusion and oxidation of the Cu wiring pattern. For example, a CrN film is formed by sputtering under specific conditions in a mixing gas atmosphere of nitrogen/argon gas. The preferred barrier film for the Cu wiring pattern has a narrow nonstoiciometric composition range of Cr:N=1:0.97-0993.

Abstract: A decoder circuit formed on an integrated circuit substrate including at least one short channel depletion transistor having a low resistance path formed between the source and the drain regions. The low resistance path is provided by an implant into the channel region that forms a depletion channel wherein the channel region has a length less than a length of a channel region of transistors in the decoder circuit that handle input/output voltage levels for the decoder circuit.

Abstract: A thermoelectric semiconductor is formed of a sintered semiconductor layer nd metal layers arranged on sides of opposite end faces of the sintered semiconductor layer. These metal layers are to inhibit a reaction between the sintered semiconductor layer and older layers through which electrodes are joined to the sintered semiconductor layer. The sintered semiconductor layer and the metal layers have been obtained beforehand by integrally sintering a semiconductor powder layer and metal sheets arranged on sides of opposite end faces of the semiconductor powder layer.

Abstract: A method is provided for forming a transistor in which capacitive coupling between the gate conductors and adjacent structures employed by the integrated circuit is reduced. According to an embodiment, a gate conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the gate conductor. A source/drain implant self-aligned to opposed lateral sidewalls of the masking structure is performed to form source/drain implant areas within the substrate. Select portions of the gate conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the gate conductor. A lightly doped drain implant self-aligned to the opposed sidewall surfaces of the narrowed gate conductor is performed to form lightly doped drain implant areas within the substrate.

Abstract: Two kinds of first and second adhesive components 8a, 8b are used to a joining treatment for connecting a protruded electrode 6 of a semiconductor element 5 and a substrate wiring 3 of a wiring substrate 1. The first adhesive component 8a is at a central portion on the surface of the semiconductor element 5 to be joined with the wiring substrate, in which the first adhesive component 8a is formed, and the second adhesive component 8b is disposed in a region at the periphery thereof having the protruded electrode 6. Further, the cure-shrinkage of the first adhesive component 8a is made greater than that of the second adhesive resin 8b and the modulus of elasticity of the second adhesive component 8b is made greater than that of the first adhesive component 8a such that the thermal expansion of the second adhesive component 8b in the high temperature circumference does not exceeds the cure-shrinkage during curing of the first adhesive 8a.

Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing an electrically conductive first layer over the node; c) providing an electrically insulative barrier second layer over the first conductive layer; d) providing a third layer over the electrically insulative barrier layer, the third layer comprising a material which is either electrically conductive and resistant to oxidation, or forms an electrically conductive material upon oxidation; e) providing an insulating inorganic metal oxide dielectric layer over the electrically conductive third layer; f) providing an electrically conductive fourth layer over the insulating inorganic metal oxide dielectric layer; and g) providing an electrically conductive interconnect to extend over the second insulative layer and electrically interconnect the first and third conductive layers.

Abstract: A multi-gate-finger MOSFET structure positions the gate element over a channel between drain and source diffusion regions, such that the entire structure is within the active region in a substrate. The gate/channel-to-drain and gate/channel-to-source diffusion edges are continuous along the gate/channel layout, so as to cascade the snap-back action to enhance uniform turn on of the entire gate element during an ESD event. In addition, the gate signal RC delay is sufficient to provide noise suppression of the output voltage when the MOSFET is used as a high current-drive CMOS output buffer.

Abstract: An integrated circuit fabrication process is provided in which copper is used as the contact plug material for a via. The via is a hole etched through an interlevel dielectric which is disposed upon a semiconductor topography, e.g., a silicon-based substrate having junctions therein. An inert implant may form an implant region within the semiconductor topography lying underneath the via. The process for forming the copper plug involves depositing a diffusion barrier upon the interlevel dielectric and within the via. Copper is then deposited via chemical vapor deposition upon the diffusion barrier such that the copper fills the entire via and forms a layer above the via. The copper is etched from all areas except from within the via, thereby forming a copper plug in the via. The resulting surface is then subjected to chemical-mechanical polishing before the diffusion barrier is removed from areas exclusive of the via.

Abstract: A spherical shaped semiconductor integrated circuit ("ball") and a system and method for manufacturing same. The ball replaces the function of the flat, conventional chip. The physical dimensions of the ball allow it to adapt to many different manufacturing processes which otherwise could not be used. Furthermore, the assembly and mounting of the ball may facilitates efficient use of the semiconductor as well as circuit board space.

Abstract: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type disposed on a surface thereof and a dielectric layer including silicon nitride disposed on the surface. The dielectric layer includes openings at least partially disposed on the p-wells. The dielectric layer also includes a top layer comprising silicon dioxide having a thickness of less than ten angstroms. Trenches having a depth comparable to or greater than a depth of the wells extend into the substrate surface within the openings. A nonconductive material is disposed within the trenches and has an upper surface that is substantially coplanar with the dielectric layer. Portions of the dielectric layer are used as gate dielectrics for transistors.

Abstract: A chip layout of a semiconductor integrated circuit, includes a plurality of device patterns that are designed to form a semiconductor substrate having a single power supply; and a metal wiring pattern, which is to be formed on the semiconductor substrate. The metal wiring pattern is divided into plural parts to provide a plurality of power-supply channels.

Abstract: A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si.sub.3 N.sub.4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.