Abstract: A pinning process including the steps of gold-plating through-holes in a laminate carrier and crimping a gold or gold-plated pin located in the through-holes to form a pin head on the top and a pin bulge on the bottom of the laminate carrier to produce a plastic pin grid array. A variety of mechanical forming processes may be employed to form the pin heads and pin bulges and cause the pin to at least partially, and preferably substantially, fill and contact the gold-plated through-hole including swage pinning, impact pinning, and double-die pinning operations. By combining the steps of gold-plating through-holes of a laminate carrier and using a mechanical pinning process to crimp a gold or gold-plated pin in the through-holes, a reliable mechanical and electrical connection may be established between the pin and the metal lines both inside and on the surface of the laminate carrier without the need for lead-containing solders and pastes.

Abstract: A high-frequency semiconductor device contains a semiconductor element in a cavity formed by a dielectric board and a cap. A first high-frequency transmission line connected to the semiconductor element is formed on the surface of said dielectric board in said cavity and a second high-frequency transmission line is formed on the bottom surface of said dielectric board, so that said first high-frequency transmission line and said second high-frequency transmission line are electromagnetically coupled together. In this semiconductor devise in which the first transmission line and the second transmission line are electromagnetically coupled together, the transmission lines need not be passed over the side wall of the cap, and neigther reflection loss or radiation loss takes place on the side wall. Besides, transmission loss of high-frequency signals is caused by neigther through-holes or via-holes, and is effectively suppressed.

Abstract: Semiconductor elements, such as driving MOS transistors, transfer MOS transistors and the like are formed in a element region defined on the surface of a semiconductor substrate. A first interlayer insulation layer is formed on these surfaces. A grounding wiring layer is formed over substantially entire surface of the first interlayer insulation layer. Also, a silicon nitride layer and a second interlayer insulation layer are formed sequentially on the surface of the grounding wiring layer. Then, a first contact hole reaching a gate electrode of the driving MOS transistor is provided at a desired position. Then, a side wall insulation layer of silicon nitride layer is formed only on the side wall surface of the grounding wiring layer facing the contact hole.

Abstract: A power FET for which it is difficult to generate oscillations dependent on the interval between adjacent pads. The power FET has a plurality of pads for first terminals, which are disposed on one side of a chip at unequal intervals, and a plurality of pads for second terminals, which are placed on the other side of the chip. Alternatively, or in addition, the plurality of pads for the second terminals may also be disposed at unequal intervals.

Abstract: A semiconductor integrated circuit is capable of reducing noise which occurs when, for example, power is removed from the circuit. The semiconductor integrated circuit includes a power wiring layer 110 used for a power conductive line 111, a first insulating layer 120 for providing electrical isolation between the power wiring layer 110 and a ground wiring layer 130 and having a through hole 121 therein enabling electrical connection between the power conductive line 111 and a first signal conductive line 151. The ground wiring layer 130 is used for each ground conductive line 132.

Abstract: A resin encapsulated semiconductor device comprises a lead frame having a center portion, a plurality of inner leads extending radially outward from the center portion, a plurality of hanger leads extending radially outward from the center portion, and a plurality of outer leads each continuous to a corresponding one of the inner leads and extending radially outward from the corresponding one of the inner leads. At a position substantially corresponding to a periphery contour of a semiconductor chip when the semiconductor chip is put on the center portion of the lead frame, each of the inner leads is cut off and divided into an inner lead inside portion and an inner lead outside portion which are separated from each other. The semiconductor chip is bonded on an island formed of the center portion of the lead frame and the inner lead inside portion of each inner lead. Each inner lead outside portion is electrically connected to a corresponding external electrode of the semiconductor chip.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.

Abstract: A device having a thin film and/or a solder ball formed on a substrate. The thin film and the solder ball each include a metal and a compound that includes an oxide, nitride, or carbide precipitate of an expandable element or a contractible element. The compound is distributed in the metal to control the tensile and compressive stresses and mechanical properties of the thin film and the solder ball.

Abstract: An apparatus and method for forming an inductor on a spherical shaped integrated circuit for use in a rectifier circuit and/or an antenna. The integrated circuit is formed around a spherical substrate and includes a conductive layer. Signal lines formed from of the conductive layer wrap around the spherical substrate to form an inductor. The inductor may be used to create a transformer or an antenna.

Abstract: A silicon chip having a mixed input/output slot structure comprising a core region having a plurality of circuits formed thereon, a wiring region surrounding and linked to the core region, and an input/output area surrounding and linked to the wiring region, where the input/output area has a plurality of input/output slots and four corner cells. The input/output slots can be divided into groups with each group having a different height, and input/output slots on the same side of the input/output area all have the same height. Therefore, a choice of sides for placing the input/output slots can be made, and the layout of input/output slots around the silicon chip is not be restricted by one side. Hence, chip size can be reduced and chip surface can be fully utilized.

Abstract: On-chip ESD protection for semiconductor chips with mixed-voltage interface applications and internal multiple power bus architecture are described. ESD robustness in shallow trench isolation 0.50- and 0.25-micron channel-length CMOS technologies is presented in the form of ESD structures and circuits including hybrid three-rail and mixed voltage interface embodiments.

Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor FET (10) includes a stoichiometric Ga.sub.2 O.sub.3 gate oxide layer (14) positioned on upper surface (16) of a compound semiconductor wafer structure (13). The stoichiometric Ga.sub.2 O.sub.3 layer forms an atomically abrupt interface with the compound semiconductor wafer structure. A refractory metal gate electrode (17) is positioned on upper surface (18) of the stoichiometric Ga.sub.2 O.sub.3 gate oxide layer (14). The refractory metal is stable on the stoichiometric Ga.sub.2 O.sub.3 gate oxide layer at elevated temperature. Self-aligned source and drain areas, and source and drain contacts (19, 20) are positioned on the source and drain areas (21, 22).

Abstract: A method of lithographically fabricating small line width features in a device in accordance with a desired pattern, the small line width features being smaller than that capable of a lithographic process alone, is disclosed. A first layer of material is provided upon a substrate, the first layer including that in which the small line width features are to be made. A lithographically patterned layer is then provided upon the first layer in accordance with a second pattern defined in conjunction with the desired pattern. The patterned layer includes a second material selected to be compatible with the material of the first layer. A conformal layer is then deposited upon the patterned layer, the conformal layer including a third material selected to be compatible in conjunction with the first material and with the second material.

Abstract: A new conceptional transistor and a method for manufacturing, which increases the integration of semiconductor devices using conventional MOS devices are provided. The present invention provides a transistor in which a structure of metal-insulator film-metal dot-metal (MIMIM), metal-insulator film-metal dot-semiconductor (MIMS), or semiconductor-metal dot-semiconductor (SMS) is formed, using junction of electrodes operating as a source and a drain having a metal dot of nm therebetween, and the current flow between source and drain is controlled by controlling tunneling and Schottky barrier formed between the source and the metal dot using the method of controlling electrical potential of metal dot through charging effect of gate electrode isolated by a thick insulator.

Abstract: A wafer configured for in-process electrical testing is disclosed. According to the invention, a single RF-device monitor is disposed partially in a first street and partially in a second street orthogonal to the first street, between four adjacent dies present on a wafer. With such an arrangement, streets having a width of 100 microns and less are suitable for accomodating a RF-device monitor having a ground-signal configuration. As a result, less space is sacrificed for device monitors than in prior art wafers, thereby increasing the amount of wafer area available for circuitry.

Abstract: A denuded zone DZ least liable to generate defects is formed in a surface layer zone 12 of a semiconductor wafer 10. In an inner layer zone 18 of the semiconductor wafer 10, micro defects BMD for gettering of impurity metal are made. In the inner layer zone 18, the precipitation of oxygen decreases with the depth. As a result, mechanical strength can be maintained while improving the gettering performance of impurity metal.

Abstract: A multilayer substrate which is fabricated by laminating a plurality of substrates, each comprising an insulation film, a plurality of via holes which pass through the upper surface to the lower surface of the insulation film, a wiring which is provided on the upper surface of the insulation film and the upper surface of the via holes and electrically connected with the via holes, a bonding member which is provided on the lower surfaces of the via holes and electrically connected with the via holes, and a bonding layer which is provided on the upper surface of the insulation film where the wiring is formed and the method of fabrication thereof whereby large costs reduction and high density effect can be obtained.

Abstract: An integrated circuit chip package (10) including a high aspect ratio integrated circuit chip (12) is disclosed. The chip (12) has a length (L1) than is greater than three times its width (L2). The chip includes a plurality of circuit functional blocks (14), each having a plurality of integrated circuit components and bond pads (16) for the input and output of signals. In one embodiment, the circuit functional blocks (14) are aligned in parallel to form a row of circuit functional blocks. The high aspect ratio integrated circuit chip (12) requires less wafer area than a comparable low aspect ratio chip, thus allowing more chips to be made from a single semiconductor wafer at a lower cost per chip. Moreover, the disclosed method for producing a high aspect ratio integrated circuit chip package (10) minimizes the risk of cracking the high aspect ratio integrated circuit chip (12) during the packaging process.

Abstract: An edge junction 10 with reduced parasitic inductance. The edge junction 10 has a laminar structure 22 including: a substrate 14; a first superconductive layer 12 deposited on a substrate 14; a first dielectric layer 16 deposited on the first superconductive layer 12; a second superconductive layer 18 deposited on the first dielectric layer 16; and a second dielectric layer 20 deposited on the second superconductive layer 18. The first and second superconductive layers 12 and 18 and the first and second dielectric layers 16 and 20 form a first laminar structure 22 having a planar segment 24 and a self-aligned ramp segment 26, the ramp segment 26 having a constantly-decreasing thickness and being connected to the planar segment 24 at an angle .theta. thereto.

Abstract: An improved leadframe structure and an improved IC package and process using such structure are disclosed. The improved leadframe structure eliminates the dambar commonly found on leadframes for use in plastic packages. A polymer structure is formed and employed primarily to act as a barrier to flashing during the epoxy encapsulation process and secondarily to provide support for the leads. The polymer structure remains a permanent part of the IC package following molding. An improved IC packaging process using the improved leadframe design eliminates common debar, dejunk and deflash operations, resulting in reduced capital costs and higher yields.