Abstract: A process for growing an ultra-thin dielectric layer for use as a MOSFET gate oxide or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density of electron traps, and impedes dopant impurity diffusion from/to the dielectric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.

Abstract: A semiconductor light emitting device includes a substrate and semiconductor overlying layers formed on the substrate. A light emitting layer is formed in the semiconductor layer so as to emit light. The substrate is transmittable of the light emitted by the light emitting layer. A light reflecting layer is formed on a part of a back surface of the substrate. As a result, a semiconductor light emitting device is obtainable by easily dividing a wafer having thereon a light emitting film through recognizing, from a wafer back side, semiconductor layer chip pattern formed overlying the main surface of the wafer.

Abstract: On manufacturing a semiconductor device, preparation is made of an organic layer (101) of a resin which has a relative dielectric constant between 1.8 and 3.5, both inclusive, and which is selected from the group consisting of a polyimide resin and a fluororesin. The organic layer has a slit. A first metal (105) is buried in the slit. A silicon oxide layer (106) containing fluorine is formed on the organic layer so that the silicon oxide layer has a hole on the first metal. A second metal (107) is buried in the hole. Preferably, an additional organic layer (101') of the resin is formed on the silicon oxide layer so that the additional organic layer has an additional slit on the second metal. In this case, a first additional metal (105') is buried in the additional slit. In addition, an additional silicon oxide layer (106') containing fluorine may be formed on the additional organic layer so that the additional silicon oxide layer has an additional hole on the first additional metal.

Abstract: This invention provides a flash memory cell structure comprising a semiconductor substrate; a tunneling oxide layer formed above the substrate and having a long narrow top profile; a gate oxide layer formed above the substrate on each side of the tunneling oxide layer; a bottom conductive layer formed above the substrate and surrounded the gate oxide layer; and a stacked gate formed above the tunneling oxide layer, the gate oxide layer and the bottom conductive layer, wherein there is an insulating layer between the stacked gate and the bottom conductive layer for electrically isolating the stacked gate from the bottom conductive layer, and that the stacked gate further comprises a floating gate, a dielectric layer and a control gate.

Abstract: The ESD protection circuit disclosed, including: a second conductivity of well formed in a predetermined portion of a first conductivity of semiconductor substrate; a first conductivity of first impurity region and second conductivity of second impurity region, formed in the second conductivity of well; a first gate electrode formed on the semiconductor substrate, and second gate electrode formed on the first gate electrode, the first gate electrode being isolated from the semiconductor substrate; second conductivity of third and fourth impurity regions, formed in a portion of the semiconductor substrate, the portion being placed on both sides of the first and second gate electrodes; and a second conductivity of fifth impurity region formed on the semiconductor substrate, the fourth and fifth impurity regions having an isolation layer therebetween.

Abstract: An electro static discharge (ESD)-protecting circuit includes a semiconductor substrate of a first conductivity type, a well of a second conductivity type formed within the semiconductor substrate, a first impurity diffusion region of the first conductivity type formed in the well, second and third impurity diffusion regions of the second conductivity type spaced apart from the first impurity diffusion region in the well, an input port connected to the first impurity diffusion region, and a ground port connected to the third impurity diffusion region.

Abstract: Formed on a grounded semiconductor substrate, via an insulation layer, is a semiconductor layer of the same conductive type as that of the substrate. Formed on the semiconductor layer are source and drain regions of the different conductive type from that of the substrate. The drain region is formed so that its portion reaches the insulation layer. A gate insulation film is formed on the semiconductor layer and a gate electrode is formed on the gate insulation film and between the source and drain regions. A conductive member is embedded in a through hole formed from a portion of the semiconductor layer to the semiconductor substrate via the insulation layer. A source electrode is formed so that the conductive member in the through hole and the source region are connected to each other by means of the source electrode. A drain electrode is connected to the drain region.

Abstract: A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes, providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak regions as an implant mask to concentrate the V.sub.T implant in the central region of the active area.

Abstract: A reticle has a transfer region and a peripheral region defined in the plane of the reticle, the transfer region being formed with a pattern to be transferred and the peripheral region being disposed surrounding the periphery of the transfer region. Reference marks for defining one virtual reference line is formed in the plane of the reticle. A transfer pattern is formed in the transfer region and includes a long linear line segment oblique to the reference line. A pair of direction designating marks is disposed in the peripheral region along a virtual straight line parallel or perpendicular to the linear line segment of the transfer pattern.

Abstract: Composition, method, and products for the environmental protection of integrated circuits comprising a robotically dispensible, wave solderable, low moisture absorbing urethane polymer reaction product of an aliphatic isocyanate, a flexibilizing low molecular weight rubbery polymer having isocyanate reactive hydroxyl terminals, and a diamine arranged to bodily encapsulate the integrated circuit within a dam of thixotropic version of the same polymer, the encapsulation being free of popcorning response to rapid heat rise after high humidity conditioning and otherwise superior as an IC encapsulant.

Abstract: In a first inter-layer insulator film above source/drain regions of basic cells constituting a gate array, first contact holes (joint contacts) are placed, so that wings (joint plates) electrically connected with the source/drain regions via plugs in those joint contacts is locally placed above the source/drain regions. Above the wings is formed a second inter-layer insulator film, above which is formed a first level interconnection which constitutes one of metal wiring layers. In the second inter-layer insulator film are formed second contact holes, so that a semi-custom ASIC is provided in which the wings and the first level interconnection are electrically interconnected via the plugs in those second contact holes. The first and second contact holes, first level interconnection, etc. are automatically designed by use of a computer based on a grid pattern in the basic cells.

Abstract: In a semiconductor device, a gate electrode is formed by sequentially forming a Schottky metal film, a barrier metal film, and a low-resistance metal film from the lower side. The Schottky metal film or barrier metal film has a gap in a lower gate vertical portion. The gap is closed at its upper and lower portions. The overlaying low-resistance metal film does not extend into the lower gate vertical portion. A method for this semiconductor device is also disclosed.

Abstract: A semiconductor chip comprises a plurality of bonding pads formed in a row along an edge of the chip and spaced at a designated gap pitch between confronting sides of adjacent pads. Each of the pads has a length perpendicular to the edge of the chip, a length distance, a width parallel to the edge of the chip, and a width distance. The length distance is different than the width distance.

Abstract: A process of manufacturing a gate stack is disclosed whereby the integrity of both the gate sidewalls and the substrate surface is maintained. Nitride spacers are constructed on the sidewalls of a gate which has been etched only to the top of the polysilicon layer. This allows more of the polysilicon sidewall to be exposed during subsequent reoxidation while at the same time minimizing effects such as bird's beak resulting during reoxidation. After the nitride spacers are constructed the subsequent etch is performed in two steps in order to minimize degradation of the substrate surface in underlying active regions.

Abstract: A geometrical layout technique for an individual circular capacitor in a semiconductor device. Circular capacitors reduce the detrimental effects of (1) corner etching, (2) peripheral capacitance, (3) capacitor to capacitor coupling, and (4) electric field anomalies and result in superior capacitor matching. The circular capacitor is comprised of a circular bottom plate made of a conducting material, a circular dielectric material coupled to the bottom plate and a circular top plate made of a conducting material.The circular capacitors may be arranged as an array in either a rectangular lattice layout or a diagonal lattice layout. These lattice layouts take advantage of the elimination or reduction of the problems encountered in the prior art such as corner etching, peripheral capacitance, capacitor to capacitor coupling and electric field anomalies.

Abstract: The MOS circuit configuration allows switching high voltages on a semiconductor chip. In order to switch a high negative voltage, for example as a programming voltage on the word line of a flash-memory, two circuit variants are given which are formed only with transistors of the same conductivity type as the substrate. The substrate and the transistors formed in the well are p-conductive. In this way it is possible to dispense with deep insulating wells which require special technology.

Abstract: A method for fabricating a bipolar device, including the steps of forming an epitaxial growth retarding layer on a substrate at a predetermined angle, forming a collector layer on the substrate so that the collector layer is adjacent the epitaxial growth retarding layer and has an inclined portion formed over an edge portion of the epitaxial growth retarding layer, forming a base layer having an inclined portion on the collector layer, and forming an emitter layer on the inclined portion of the base layer.

Abstract: A semiconductor component includes a semiconductor body having a front side, a rear side and at least one curved side surface. As viewed from outside the semiconductor body, the at least one curved side surface is convex adjacent the rear side and concave adjacent the front side. The rear side has a greater area than the front side. A method is also provided for producing a plurality of the semiconductor components.

Abstract: Electrostatic discharge protection device is provided that protects the gate insulating layer without using an additional circuit to lower the trigger voltage of a thyristor. The electrostatic discharge protection device includes first and second impurity regions of a bipolar transistor being spaced a predetermined distance apart in a first conductivity type semiconductor substrate, and first and second impurity regions of a field transistor perpendicular to and along both sides of the first and second impurity regions of the bipolar transistor. A gate line formed between the first and second impurity regions of the bipolar transistor on the semiconductor substrate is coupled to one of the impurity regions of the field transistor. A Vss line is coupled to the other impurity region of the field transistor. The Vss line is also coupled to the first impurity region of the bipolar transistor. A metal layer is coupled to the first impurity region of the bipolar transistor and a pad.

Abstract: A gate array basic cell and circuit layout architecture for efficiently routing power supply traces. A basic cell has one or more transistors PMOS and one or more NMOS formed by diffusion regions and gate regions. A portion of the diffusion region extends outward to a point past the end of the gate region. Basic cells are arranged in rows with each basic cell having its p-type diffusion region extending in a direction opposite the n-type diffusion region. Basic cells are arranged in rows. Power supply traces are placed between rows, across the extended diffusion regions. Adjacent rows are shifted with respect to each other. A power supply trace is shared by adjacent rows of basic cells such that a connection can be made between the power supply trace and the extended diffusion regions without additional routing.