Abstract: A method for replacing defective elements of a memory array. The method includes forming a first redundant circuit, which in turn includes forming a first plurality of address fuses. The first plurality of address fuses are configured to specify, when set, an address of one of the defective elements. The method further includes forming a first plurality of address latches, respective ones of the first plurality address latches being coupled with respective ones of the first plurality of address fuses. There is further included forming a first redundant element. Additionally, the method includes forming a first decoding logic circuit. The first decoding logic is coupled to the first plurality of address latches and the redundant element.

Abstract: A memory device includes an array of memory cells arranged in rows and columns. A row-address decoder allows a row address to propagate therethrough while a row address strobe is at an inactive logic level. In response to a transition of the row address strobe from the inactive level to an active level, the decoder enables a row of memory cells selected by the row address. A row-address latch stores the row address in response to the transition of the row address strobe. The memory device may also include a transition detector that monitors the row address for a transition thereof. A delay circuit is coupled to the decoder, the latch, and the detector. If the monitor detects a transition of the row address, the delay circuit delays the enabling of the row of memory cells and the storing of the row address at least predetermined time after such a transition.

Abstract: A single in-line memory module (SIMM) having on-board regulation circuits is disclosed. The present invention includes a plurality of inputs. These inputs include a first reference voltage signal. The present invention employs a plurality of memory elements that are arranged to form a datapath having a predetermined width. These memory elements operate at a second reference voltage signal that is different from the first reference voltage signal received by the SIMM. On-board regulation circuits are provided to translate the first reference voltage signal into the second reference voltage signal so that the memory elements of the SIMM can use the first reference voltage signal. A driver for providing an interface between the memory elements and a computer system is also provided. This driver may also operate at the second reference.

Abstract: One memory array is divided into a plurality of banks sharing a row of memory cells. Global IO buses are disposed for memory column blocks forming the plurality of banks included in one memory array. The global IO buses are selectively and electrically connected to the same data input/output terminal.

Abstract: A five transistor memory cell, is a single ended static random access memory (SRAM) cell. Reading and writing from the cell is implemented with one bit line along with word line read and word line write signals. One of the transistors within the memory cell is not coupled directly to ground, but is instead coupled to a controlled impedance node. This permits the affected transistor to float between ground and a high impedance state, which permits one bit line to write into the memory cell.

Abstract: A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so that bonding pads in the metal layer are eliminated.

Abstract: A small, lightweight zoom lens has high imaging performance with a large aperture and a large zoom ratio. The zoom lens includes a first lens unit having positive power, a second lens unit having negative power, and a third lens unit having positive and negative power components. During zooming, the second lens unit moves along the optical axis and the first lens unit is fixed. At least one of the lens surfaces of the first or second lens units is aspheric. The first lens unit has at least one positive lens component with refractive index Nd+ and Abbe number .upsilon.d+ that satisfies the following condition:Nd+<1.43795<.upsilon.d+.

Abstract: A long focal length microlens system that controls the variation of the aberration from the infinite object distance to shooting at equal magnification. The long focal length microlens system includes a first lens group G1 of positive refractive power a second lens group G2 of positive refractive power and a third lens group G3 of negative refractive power. When focusing from a infinite object distance to a close shooting distance, a value of D1 is reduced while a value of D2 is increased and a condition of 0.16<.vertline..DELTA.D1 .vertline./.DELTA.D2<0.5 is satisfied where D1 is a gap of lens apexes between said first group G1 and the second group G2. D2 is a gap of lens apexes between said second group G2 and the third group G3, .DELTA.D1 is (D1 at any object distance)-(D1 in the infinite object distance) and .DELTA.D2 is (D2 at any shooting distance)-(D2 in the infinite object distance).

Abstract: A non-volatile memory device having optimized management of data transmission lines, having the particularity that it comprises at least one bidirectional internal bus that runs from one end of the memory device to the other, one or more source structures that exist externally and internally to the memory device, and a timer means. The timer means is adapted to time-control the independent and exclusive access of the external and internal source structures, within a same memory cycle, to the internal bus for the transmission of data, controls, and functions, from one end of the memory to the other over the internal bus.

Abstract: A memory cell array includes a first memory cell, a second memory cell, and a bit line which extends between the first and second memory cells. During normal operation, the bit line is used as a write path for data values to be written to the first and second memory cells. If the first memory cell is defective, the bit line is used to route the data value stored in the second memory cell to the first memory cell, effectively replacing the first memory cell with the second memory cell. In another embodiment, a memory cell array includes a first memory cell for storing a first data value and a second memory cell for storing a second data value. A first pair of bit lines are coupled to the first memory cell, and the first data value is written to the first memory cell on the first pair of bit lines. A second pair of bit lines are coupled to the second memory cell, and the second data value is written to the second memory cell on the second pair of bit lines.

Abstract: A matrix memory with improved virtual ground architecture and evaluation circuit from which the informational content of two neighboring memory cells can be simultaneously read at a bit line during a read event. The memory cells with information "0" are realized, for example, by a respective field effect transistor with low threshold voltage. Every bit line provided for the readout is connected to the drain terminals of two neighboring field effect transistors in the same row. The source terminals are applied to one of two potentials that differ from one another. Depending upon which of the field effect transistors is conductive upon selection of the pertinent word line, different resultant potentials are obtained on the bit line. Such potentials are then converted in the evaluation circuit into binary signals that represent the read information.

Abstract: A memory cell in which data is written and read from a pass gate. The memory cell has a connection to a first pass gate, connecting the memory cell to a bit line. Additionally, the memory cell has a second pass gate connecting the memory cell to a complementary bit line. The pass gates are controlled by a word line and a complementary word line.

Abstract: A method for programming multiple values in an individual flash memory cell is disclosed. An individual flash cell is programmed by holding the bit line, corresponding to the particular memory cell to a value, V.sub.d, while the voltage on the control gate, V.sub.g, of the memory cell is varied. By varying the voltage on the control gate, multiple values are stored in the memory cell. The resulting values are self-convergent, therefore, verify circuitry becomes unnecessary.

Abstract: A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific basing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplied the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.

Abstract: A static random access memory device (SRAM) keeping a resistance value of a resistance element at a predetermined level regardless a process variation, by improving a special margin of a diffusion layer region at which the resistance element is formed and a node for connecting a gate electrode thereto. In the SRAM, there is provided a diffusion layer region in a substrate, having a first part of which may form a the resistance element, a second part of which is connected to the drain or source of the MIS access transistor, and a third part of which is connected to the source or drain of the MIS driver transistor and is defined the node, and there is provided an electrode layer connecting the gate of the MIS driver transistor and the node in the diffusion layer region.

Abstract: A semiconductor integrated circuit is provided in which a differential amplifier circuit such as a sense amplifier is operated at high speed even if the operating voltage is reduced. To achieve this, a MOS transistor for supplying the operating voltage to a drive line on the high-potential side of a differential amplifier circuit is of N-channel type and the amplitude of a switching control signal for controlling this transistor is the potential of the step-up voltage produced by stepping up a supply voltage in level. The output voltage of an internal step-up circuit for achieving a word-line selection level is utilizable as the step-up voltage.

Abstract: By setting full group reversal control gates to a logical voltage "H", memory cells on all bit lines of a memory cell array block are connected to a reversal voltage supply circuit so that a group reversal operation is performed. When one of the group reversal control gates is set to the logical voltage "H", the memory cells on the bit lines having either even or odd numbers of the memory cell array block are connected to the reversal voltage supply circuit so that a partial group reversal operation is performed. When one of column selection gates is set to the logical voltage "H", the selected bit line is connected to the reversal voltage supply circuit. Consequently, a line reversal operation for the memory cell connected to the selected bit line is performed. Thus, the high-speed reversal operation which fully controls the offleak current of the memory cell can be implemented and the low-voltage operation can be realized by changing the operation unit for performing the reversal operation.

Abstract: A memory device is described which uses dynamic digitline sensing where separate plate lines are provided for each digitline of a memory cell array. A voltage of the plate line is dynamic in that it changes during read operations to create a larger differential for sensing stored data. A method is described which uses either an inactive digitline or a simulation circuit to perform an equilibration operation. Thus, the memory uses an inactive digitline for equilibration which is not necessary for data sensing.

Abstract: A data output circuit includes a ground terminal, a power supply terminal, an output terminal having parasitic capacitor, a PMOS transistor having a current path connected between the power supply terminal and the output terminal and a gate to which one of first and second complementary data signals is supplied, an NMOS transistor having a current path connected between the ground terminal and the output terminal and a gate to which the other of the first and second complementary data signals is supplied, and a gate control section for feeding back the potential of the output terminal to the gates of the transistors and to change the potential of the output terminal toward a predetermined intermediate level within the voltage ranged between the ground terminal and the power supply terminal before the first and second complementary data signals are supplied.

Abstract: In a DRAM, an external cycle count circuit detects an operation cycle of a signal RAS which is externally inputted, and a signal expressing the result is outputted to a CBR signal generating circuit and a self refresh signal generating circuit. In response to outputs from the respective signal generating circuits, an internal RAS signal generating circuit outputs a refresh instruction signal INRAS for CBR refresh and self refresh. For self refresh, as the operation cycle of the signal RAS immediately before self refresh begins, a refresh cycle is set longer. For CBR refresh, when the operation cycle of the signal RAS is long, a CBR refresh instruction signal is generated in accordance with only a part of an operation of the signal RAS. By reducing the frequency of refresh, consumption power is reduced. By means of control which considers a parameter which influences an internal temperature of a semiconductor memory device such as a DRAM, consumption power is reduced and an operation speed is improved.