Abstract: A magnetic tunnel junction (MTJ) device is usable as a magnetic field sensor or as a memory cell in a magnetic random access (MRAM) array. The MTJ device has a "pinned" ferromagnetic layer whose magnetization is oriented in the plane of the layer but is fixed so as to not be able to rotate in the presence of an applied magnetic field in the range of interest, a "free" ferromagnetic layer whose magnetization is able to be rotated in the plane of the layer relative to the fixed magnetization of the pinned ferromagnetic layer, and an insulating tunnel barrier layer located between and in contact with both ferromagnetic layers. The pinned ferromagnetic layer is formed as a sandwich of two antiferromagnetically coupled ferromagnetic layers separated by a metallic layer. The free and pinned ferromagnetic layers are located in separate spaced-apart planes so as to not overlap the tunnel barrier layer.

Abstract: A semiconductor memory device capable of shortening data reading time in a first read cycle after the mode has been changed from a write mode to a read mode while maintaining high-speed cycle time when data is written despite simple structure, the semiconductor memory device having a memory cell array having a plurality of dynamic memory cells, to which data can be written, data line pairs to which data read from the memory cells and data which must be written on the memory cells are transferred, a write driver for driving the data line pairs in accordance with write data supplied from outside when data is written to the memory cells and an equalizing circuit for setting the data line pairs to an intermediate potential whenever the data line pairs are operated by the write driver.

Abstract: Data input/output pad portions are arranged corresponding to memory blocks and adjacent to a corresponding memory block in the center region between memory blocks, and memory blocks. Power supply pads are arranged at both ends of the center region. Power supply pad transmits a power supply voltage to data input/output pad portions, and power supply pad transmits the power supply voltage to data input/output pad portions. Power supply pad for peripheral circuitry is arranged in the center portion of the center region. A multibit test circuit is provided for each memory block. A data input/output buffer operating stably at high speed is implemented in a large storage capacity memory device which in turn accommodates a multibit test mode.

Abstract: An input buffer circuit includes a first amplifier causing a first change in an output signal by detecting a rising edge of an input signal, a second amplifier causing a second change in the output signal by detecting a falling edge of the input signal, and a feedback path feeding back the output signal as a feedback signal to the first amplifier and the second amplifier. The feedback signal controls the second amplifier such that a timing of the first change only depends on the first amplifier, and controls the first amplifier such that a timing of the second change only depends on the second amplifier.

Abstract: Improved apparatus for low cost measurement of spectral intensity distribution of light energy reflected from surfaces of or transmitted through objects or materials, using solid state emitters and detectors. The measurement results remain consistent in spite of variations in component characteristics or temperature.

Abstract: A non-volatile semiconductor memory device includes first, second and third comparators, counter and ring oscillator. The first comparator compares an input address with an access inhibition address. The counter counts the number of changes of addresses input after coincidence of the addresses when the first comparator detects the coincidence of the addresses. The second comparator compares the count number of the counter with a preset count number and operates the ring oscillator when the count numbers coincide with each other. The third comparator compares the cycle number of the ring oscillator with a preset cycle number and scrambles the input address to output error data when the cycle numbers coincide with each other.

Abstract: A memory cell of an SRAM includes an access transistor, and an MIS switching diode. The access transistor has a drain electrode connected to a bit line of a corresponding column, a source electrode connected to a storage node, and a gate electrode connected to a word line of a corresponding row. The threshold voltage of the access transistor is small than the threshold voltage of a bit line load transistor. The MIS switching diode is connected between the storage node and a second power supply potential node. The switching initiate voltage of the MIS switching diode is greater than the difference between the first potential and the threshold voltage of the bit line load transistor, and smaller than the difference between the first potential and the threshold voltage of the access transistor. Thus, data can be read/written and held accurately.

Abstract: A SRAM storage cell has a NMOS transistor and a PMOS transistor connected with each other between a source of potential and ground. The sources, gates and gate back plates of the transistors are commonly connected and coupled to a storage node. The drain of the NMOS transistor is supplied with the potential, whereas the drain of the PMOS transistor is grounded. A pass NMOS transistor is connected between the storage node and bit and word lines. This storage cell configuration provides considerably reduced area compared to conventional static storage cells.

Abstract: The present invention discloses a mask defect inspection apparatus for optically detecting a defect on a mask having a circuit pattern, which comprises an illumination system for illuminating the mask with inspection light; a first light receiving optical system for receiving the inspection light reflected by the mask; a second light receiving optical system for receiving the inspection light transmitted by the mask; a first spatial filter for shielding the inspection light passing through a central region including the optical axis of the first light receiving optical system in an optical Fourier transform plane for the circuit pattern in the first light receiving optical system; a second spatial filter for shielding the inspection light passing through a central region including the optical axis of the second light receiving optical system in an optical Fourier transform plane for the circuit pattern in the second light receiving optical system; a first detector for photoelectrically converting the inspecti

Abstract: An iridium oxide local interconnect method for a ferroelectric memory cell includes the steps of forming a conductive layer that extends from a source/drain contact of the transistor proximate to an electrode contact of the ferroelectric capacitor and forming an iridium oxide local interconnect extending from the source/drain contact of the transistor to the electrode contact of the ferroelectric capacitor. The conductive layer is laterally terminated not less than one-half micron from the electrode contact of the ferroelectric capacitor. The conductive layer can include an upper iridium layer and a bottom titanium nitride layer, or can include a single layer of completely reacted titanium nitride. After the local interconnect is formed a top oxide layer is deposited. A late recovery anneal is then performed in oxygen at an elevated temperature to rejuvenate the electrical characteristics of the ferroelectric capacitor. Finally, a bit line contact is opened and metalized.

Abstract: In a motor controller circuit, an integrated circuit driver drives a plurality of switching transistors which are organized along a top rail and a bottom rail. To reduce the conduction of current through the parasitic diode D.sub.S1 of the integrated circuit, the switching transistors at the bottom rail are provided with individual Kelvin emitter connections, which reduce the parasitic internal inductances, which otherwise produce highly negative voltages when the top rail transistors are turned off. Further, individual traces are provided on the printed circuit board from the COM terminal to the Kelvin emitters. Finally, a small resistance is provided in series with each Kelvin emitter connection which increases the resistance in series with the parasitic diodes and hence reduces the current flowing in the parasitic diodes.

Abstract: A data storage device including a substrate, a data storage layer on the substrate, and a spin-polarized electron source. The data storage layer comprises a fixed number of atomic layers of a magnetic material which provide the data storage layer with a magnetic anisotropy perpendicular to a surface of the data storage layer. A data magnetic field is created in the data storage layer. The data magnetic field is polarized either in a first direction corresponding to a first data value or in a second direction corresponding to a second data value.

Abstract: Reading circuit for multilevel non-volatile memory cell devices having, for each cell to be read, a selection line with which is associated a load and a decoupling and control stage with a feedback loop which stabilizes the voltage on a circuit node of the selection line. To this node are connected a current replica circuit which are controlled by the feedback loop. These include loads and circuit elements homologous to those associated with the selection line of the memory cell and have an output interface circuit for connection to current comparator circuit.

Abstract: A read-only memory structure, having a three dimensional arrangement of memory elements, is disclosed. The memory elements are partitioned into multiple memory levels. Each memory level is stacked on top of another. Within each memory level, there are a plurarity of memory elements and address select lines. The memory elements can be either mask programmable or electrical programmable.

Abstract: The present invention is a method and apparatus for reading a storage cell configured in a negative feedback mode to provide linear variation of cell current with the threshold of the cell. The apparatus comprises a floating gate storage cell having a source, a gate, a floating gate and a drain. The source of the floating gate storage cell has a first predetermined reference voltage and the gate of the floating gate storage cell has a predetermined second reference voltage. The apparatus also comprises first circuitry driving the voltage on the drain of the floating gate storage cell to a third predetermined reference voltage, the first, second and third predetermined reference voltages being selected to not change a threshold voltage of the storage cell. The apparatus further comprises second circuitry providing an output proportional to the current passing through the floating gate storage cell while the first, second and third predetermined reference voltages are applied.

Abstract: A page mode flash memory or floating gate memory device, includes a page buffer based on low current bit latches. The low current bit latches enable efficient program, program verify, read and erase verify processes during page mode operation. The array includes bit lines coupled with corresponding columns of cells in the array, and wordlines coupled with corresponding rows of cells in the array. Bit latches are coupled to respective bit lines to provide a page buffer.

Abstract: A test circuit is provided for detection of data retention faults and cell stability faults of a memory array, such as a static random access memory (SRAM). The memory array test circuit comprises a weak write test circuit, a memory array address decoder, a microprocessor and display unit. During testing of the memory array, the weak test circuit controls the address decoder to decrease the voltage on the word lines so that it is less than the threshold voltage of the memory array transistors. The microprocessor then writes an inverted data to the memory array and then reads it. The read inverted data is sent to the display unit for comparison with a known template. By comparing the read inverted data to the template, defective memory cells can be identified.

Abstract: A semiconductor memory device includes: subarrays having memory cells each arranged at cross points of a plurality of bit lines and a plurality of word lines; a row decoder for selecting among the word lines; a column decoder for supplying a select signal to transfer gates for selecting among paired bit lines; and a clamping circuit for fixing the potential of a column select line at a constant potential before the column decoder is activated.

Abstract: A semiconductor memory has a bit line connected to a plurality of memory cells and a single end type sense amplifier connected to the bit line. The single end type sense amplifier has an invertor whose input node is connected to the bit line, a precharge circuit precharging the bit line in response to a precharge signal, a control signal generator generating a control signal in response to an output signal from the invertor, and a discharge circuit discharging the bit line in response to the control signal.

Abstract: Ferroelectric memory devices contain an array of ferroelectric memory cells therein and control circuits for enabling the performance of nondestructive read operations. The memory cells of a device contain a ferroelectric memory cell and each memory cell contains a ferroelectric capacitor having a first electrode electrically coupled to a plate line and an access transistor electrically coupled in series between a bit line and a second electrode of the ferroelectric capacitor. A decoder circuit is also provided. The decoder circuit is electrically coupled to the access transistor of the memory cell by a word line and performs the function of, among other things, turning on the access transistor during a read time interval.