Abstract: An equilibration driver circuit provides an equilibration signal on a node in a dynamic random access memory (DRAM). The node is coupled to an equilibration circuit in the DRAM which equalizes voltage levels on complementary pairs of input/output lines in the DRAM in response to the equilibration signal. The equilibration driver circuit comprises an address transition detection circuit having an input terminal adapted to receive a column address signal. The address transition detection circuit is operable to output a pulse signal having a predetermined duration in response to a transition of the column address signal from one logic level to the complementary logic level. A switching circuit has an input terminal receiving the pulse signal and an equilibration terminal coupled to the node. The switching circuit is operable in a first mode to couple the equilibration terminal to a first reference voltage in response to the pulse signal being active.

Abstract: A method and apparatus for testing redundant circuitry within a memory array is provided. A control unit is described to interface a memory array to a wafer tester to selectively enable redundant rows/columns within a memory array during wafer test, without requiring permanent alteration of row/column select switches. Temporary enabling of redundant rows/columns allows testing of redundancy prior to alteration of the permanent switch logic. The control unit, upon command from a wafer tester, selectively enables particular redundant rows/columns to allow those redundant rows/columns to be tested. After testing, if the redundant rows/columns repair memory defects, permanent switch logic may be altered, without requiring further testing of the redundant circuitry.

Abstract: Respective ones of a plurality of memory array blocks are rendered drivable independently of each other under control of an array activation control circuit. When data is read from one array block under control of the array activation control circuit, the data can be transferred to another array block by selecting and coupling a column in the other array block to a global I/O bus.

Abstract: A self timed precharge sense amplifier for allowing high speed reading of a memory cell of a memory array. The self timed precharge sense amplifier uses a precharge device for generating an output voltage which is used to ramp up a voltage level of a column of the memory array where the memory cell is located. State control circuitry is coupled to the precharge device for activating and deactivating the precharge device. A sense amplifier is coupled to the precharge device and to the state control circuitry for monitoring the output voltage of the precharge device and for signalling the state control circuitry to deactivate the precharge device when the output voltage has reached a threshold voltage level set by the sense amplifier which is a minimum amount of voltage required to properly read the memory cell.

Abstract: A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.

Abstract: A flat NOR type mask ROM includes a plurality of bit-lines that are parallel to each other, a plurality of memory cells provided between adjacent bit-lines and a plurality of word-lines that are parallel to each other and orthogonal to the bit-lines, each word-line being connected to a plurality of the memory cells. The memory cells provided every predetermined number of bit-lines are OFF-cells which are always in an OFF state regardless of a potential level of the respective word-line.

Abstract: A method and apparatus for implementing a prefetch scheme in which a plurality of data are simultaneously read from memory cells of sequential addresses synchronized to an external signal and serially transferred from the memory cells to a temporary latch circuit which has a number of bits corresponding to the member of bits in the prefetch scheme. The bits in the temporary latch circuit are multiplexed and sequentially driven out of the memory device. The memory device includes a plurality of memory cells which are connected to an input/output line pair through a plurality of column select gates, each of which is controlled by an independent chip select line. A sense amplifier is connected to the input/output line pair for sensing and amplifying data from the input/output lines and to transmit data to the input/output lines. A data output buffer transfers the data from the sense amplifier to the outside of chip.

Abstract: Systems and methods for steering a complex, spatially-modulated incident beam of coherent light to gain access to data locations in a holographic memory cell (HMC). One of the systems includes: (1) a reflective element, locatable proximate a first focal plane of the incident beam, (2) a rotational steering mechanism, coupled to the reflective element, that orients the reflective element according to a desired rotational angle to steer the incident beam in a desired direction and (3) a refractive element that refracts the beam reflected from the reflective element to create a second focal plane for the beam, the HMC locatable proximate the second focal plane and rotatable about an axis of a plane thereof to receive the beam at a location thereon that is a function of the desired direction and an angular position of the HMC.

Abstract: A synchronous memory device is described which uses unique column select circuitry. The memory device pipelines address decode and column select operation to increase clock frequency. The column select circuitry includes latches and coupling circuits. The latches are used to latch a column select circuit. The coupling circuit isolates a column select signal from the memory cell columns until an enable signal is provided. The address decode can be combined with an enable signal to reduce the total number of latch circuits needed for a bank of memory cells.

Abstract: A mounting assembly (50) for an electro-optic modulator array (10) is disclosed. Electro-optic modulator array (10) is mounted on a ledge (52) of wiring board (53). A recess (51) in wiring board (53) allows electrical connection of electrodes (14,15) from both a first surface of electro-optic modulator array (10) to a first side of wiring board (53), and from a second surface of electro-optic modulator array (10) to a second side of wiring board (53). A resilient adhesive (54) is used to attach electro-optic modulator array (10) to board (53). Wiring electro-optic modulator array (10) to both sides of wiring board (53) allows full utilization of the PLZT substrate and hence, higher light beam density per unit length.

Abstract: An optical memory system includes memory cells which utilize synthetic DNA as a component of the information storage mechanism. In the preferred embodiment, memory cells contain one or more chromophoric memory units attached to a support substrate. Each chromophoric memory unit comprises a donor, an acceptor and, at some time during its existence, an active quencher associated with the donor and/or the acceptor. The donor and the acceptor permit non-radiative energy transfer, preferably by Forster energy transfer. To write to the memory cell, the quencher is rendered inactive, preferably by illumination with ultraviolet light. To read, the chromophoric memory units in a read portal are illuminated, and the read illumination is detected. In the preferred embodiment, multiple chromophoric memory units having resolvable read properties are contained within a single read portal. In this way, a multibit word of data may be read from a single diffraction limited read portal.

Abstract: A memory device (10) for use in an electronic system (12). The system (12) includes a processor (16) that produces a plurality of control signals. The memory device (10) includes a memory array (18) coupled to receive control signals from the processor (18). The memory device (10) also includes a pulse generator (22) that receives at least one of the control signals from the processor (16). The pulse generator (22) includes a latch formed from, for example, a cross coupled pair of NAND-gates (32 and 34). A delayed signal from the latch is coupled to control the reset of the latch such that the latch of the pulse generator (22) outputs a modified control signal for the memory device (10) that has a pulse with a width that is at least as long as the delay.

Abstract: A zoom lens is provided such that it has a high image quality over its entire zooming range, an angle of view of 70.degree. or greater at a wide-angle end, a zooming ratio of 2.5 or greater, and an F-number of about 2.8 throughout the entire range. The zoom lens has a first lens group having a negative refractive power, a second lens group having a positive refractive power, a third lens group having a negative refractive power, and a fourth lens group having a positive refractive power. The first, second, third and fourth lens groups are arranged in order from the object side of the zoom lens. The zoom lens also has an aperture stop. The third lens group has at least one concave aspheric surface. During zooming, at least the first, second and fourth lens groups are moved along the optical axis. The zoom lens satisfies the condition 0.5<(A.sub.w /l.sub.w)/(A.sub.t /l.sub.t)<1 when A.sub.

Abstract: A moire interferometry system and method are provided for achieving full field surface contouring with an extended depth of view of image. The moire interferometry system includes a projection system generally made up of a light source, imaging lens and a square wave grating pattern. The imaging lens is configured to filter higher order light rays passing through the square wave grating pattern so as to project a sine wave like pattern onto a desired surface. The moire interferometry system also includes a viewing system generally made up of an imaging lens, a submaster grating and a camera. The submaster grating is preferably a customized grating that may be produced by recording a grating pattern in relation to a reference surface. The camera is able to view an image anywhere within the extended depth of image and analyze the moire fringes. A determination of deviation between a test part and a reference surface provides a part inspection system.

Abstract: A memory system having split logical bit lines and interleaved pre-charge/access cycles is provided. A bit line access circuit supports multiple conductors per logical bit line and pre-charges the conductors before access cycles thereto. The access cycles for one logical bit line are performed simultaneous with the pre-charge cycles for another logical bit line by the access circuit. Virtual reading is provided for eliminated memory cells. The memory system can be used in a programmable gate array having memory cells distributed throughout for programming respective programmable resources.

Abstract: An apparatus and method which sequentially selects subsets of data bits read in parallel from an array of memory cells (each cell being operated as a multistate memory device) and sequentially asserts the selected subsets to a data bus. Preferably, the cells are flash memory cells. Preferably, the apparatus includes a sense amplifier circuit, a multiplexer, and circuitry operable to read a number (N) of the cells in parallel, whether the cells are operated as binary or multistate devices. The sense amplifier has N input lines and MN output lines, where M is the number of binary bits in a binary representation of the data read from each cell operated as a multistate device. The multiplexer has MN inputs (each connected to one of the output lines of the sense amplifier circuit), N outputs connected to a data bus having N-bit width, and is controllable to output selected N-bit subsets of the MN bits received at its MN inputs.

Abstract: In a dynamic random access memory, a sense amplifier has direct sense circuitry (MNRD, MNRD.sub.--, MNYSR, MNYSR.sub.--, MNYSW, MNYSR.sub.--) included therewith to minimize the effect of the parasitic impedances of the local INPUT/OUTPUT lines RES.sub.-- LIO, RES.sub.-- LIO.sub.--). The WRITE-ENABLE signal and the READ-ENABLE signal are each combined with the Y-SELECT signal to provide a Y-SELECT-READ and a Y-SELECT-WRITE signal. Each of these two signals, along with their complementary logic signals, control a transistor pair (MNYSR, MNYSR.sub.-- ; MNYSW, MNYSR.sub.--) in the direct sense circuitry, coupling the sense amplifier and the local INPUT/OUTPUT lines (RES.sub.-- LIO, RES.sub.-- LIO.sub.--). Because the original signal set had three enabling signals (along with their complements), the present implementation eliminates a transistor pair in the direct sense circuitry.

Abstract: An integrated memory circuit is described which can be operated in a burst access mode. The memory circuit includes an address counter which changes column addresses in one of a number of predetermined patterns. The memory includes generator circuit for generating an internal control signal based upon external column address signals. The generator circuit detects the first active transition of the column address signals and the first inactive transition of the column address signals.

Abstract: In a DRAM, an upper address is assigned to each of ways W0 and W1, and a lower address is assigned to each word line WL in each of ways W0 and W1. A self-refresh start trigger generating circuit senses start of self-refresh, and a refresh address change sensing circuit senses change in an upper address. Based on the result of sensing, way selection signals RX0 and RX1 will not be reset and held at an active level while ways W0 and W1 are selected, respectively. Consequently, power consumption can be reduced compared to a conventional example in which signals RX0 and RX1 are reset every time a single word line WL is selected.

Abstract: A memory device includes input and output data sequencers that transfer data between a memory array and a data bus where transfers between the data sequencers and the data bus are controlled by a first clock signal and transfers between a memory array and the data sequencers are controlled by a second clock signal of arbitrary phase relative to the first clock signal. Each data sequencer includes two or more sets of interim latches that each latch a portion of the data in a staggered fashion. One portion of the interim latches latch data while another portion transfers data to the data bus or the memory array. Because the data is segmented into portions and each portion is activated separately, the data can be transferred quickly without data collisions.