Abstract: A non-volatile, integrated circuit memory, such as a Flash EPROM, including an array 1 of memory cells 10, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. Included is a decoder circuit 16 having a plurality of input lines 94, 96, for each row in the array, and having as outputs the row lines 15. The decoder circuit includes a decoder logic circuit associated with each row line, the decoder logic circuit including a plurality of low power logic devices 84-90 interconnected to perform a predetermined decoding function on the signals on the input lines for the associated row line to apply a signal to an associated row node when the decoder logic circuit determines that the associated row line is selected.

Abstract: A circuit and method for providing a plurality of voltage regulators whose outputs are constant for ranges of different external voltages are disclosed. The voltage regulators are made to be adaptable to two different ranges of external voltages through use of a master-slice technique. Furthermore, in a first voltage regulator, the supply current capability of the regulator is significantly increased under very low external voltage conditions. In a second voltage regulator, the voltage level on any node of the regulator does not exceed a voltage level that is too high, yet still sinks most of its current from the external power supply. A third voltage regulator is able to charge and discharge its output voltage so that it will maintain at a constant level. Finally, a fourth voltage regulator is optimized to reduce dielectric leakage.

Abstract: A programming circuit programs an anti-fuse having first and second terminals with the programming circuit and the anti-fuse being fabricated in the same integrated circuit. The programming circuit includes a first external terminal of the integrated circuit coupled to the first terminal of the anti-fuse. The first external terminal is adapted to receive a first programming voltage having a predetermined polarity. A second external terminal of the integrated circuit is adapted to receive a second programming voltage having a polarity opposite that of the first programming voltage. A voltage translation circuit is coupled between the second external terminal and the second terminal of the anti-fuse and includes an enable terminal adapted to receive an enable signal. The voltage translation circuit is operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active.

Abstract: An overvoltage tolerant CMOS tristate output buffer capable of withstanding tristate overvoltages without reverse currents or latch-up, the output buffer having a stabilized protection circuit for driving the N-well and gate of the P-channel driver transistor to the output pad voltage when the output pad voltage becomes excessive. The stabilized protection circuit includes a hysteresis circuit for controlling switch transistors which bias the N-well. The presence of the hysteresis circuit causes the protection circuit to have an input hysteresis characteristic, thus preventing excessive switching of the N-well biasing transistors when the output pad voltage varies near the output buffer power supply voltage during tristate.

Abstract: A semiconductor memory device includes a delay stage for delaying a row address strobe signal ZRAS by a predetermined time, a first signal generating circuit for generating a signal instructing activation/precharge of an array in accordance with the row address strobe signal ZRAS, and a second signal generating circuit for generating a signal setting the output stage to an output high impedance state in accordance with a delayed row address strobe signal ZRAS from the delay stage and a column address strobe signal ZCAS. Even if both the column address strobe signal and row address strobe signal may be simultaneously set to the high and low levels, respectively, the column address strobe signal and the delayed row address strobe signal are not simultaneously set to the high level, so that the output stage is prevented from attaining the high impedance state, and data output is allowed. Therefore, the semiconductor memory device can operate fast with a low current consumption.

Abstract: A static semiconductor memory device includes a semiconductor substrate, first and second load transistors located along a first power line, and first and second drive transistors located along a second power line. The device further includes first and second select transistors, a first connection line, a second connection line, and a capacitor. The first connection line is commonly connected a gate of the first load transistor and a gate of the first drive transistor to drains of the second load transistor, the second drive transistor and the first select transistor. The second connection line is commonly connected a gate of the second load transistor and a gate of the second drive transistor to drains of the first load transistor, the first drive transistor and the second select transistor. The capacitor is supplemented with at least one of the first connection line and the second connection line.

Abstract: A ferroelectric memory device has a ferroelectric memory capacitor with a hysteresis characteristic adapted to store either a first memory content corresponding to a first polarization condition or a second memory content corresponding to a second polarization condition when there is no applied voltage. A first load capacitor is connected in series with the memory capacitor, and a second load capacitor is connected in series with a reference capacitor. The first and second capacitors are both ferroelectric capacitors and have substantially the same characteristics as the memory capacitor.

Abstract: A semiconductor device which allows an input signal thereto to select one of N operation modes, and operates in the one of N operation modes includes a selection circuit for selecting an operation mode from the N operation modes when the input signal indicates the operation mode, and for selecting a predetermined operation mode from the N operation modes when the input signal is an undefined signal indicating none of the N operation modes. The semiconductor device further includes an internal circuit operating in an operation mode selected by the selection circuit.

Abstract: A memory array comprising a number of memory cells, a set path, a signal path, and at least one word line for transmitting a word line select signal to a row of the memory cells. The word line extends from a first driver end to a second end. The memory array further includes a dummy word line extending from the first driver end to a point between the first and second ends and back to the first end for transmitting a tracking signal responsive to the word line select signal. By folding the dummy word line in this manner, improved tracking of the set path with the signal path is achieved.

Abstract: A method for improving the endurance and reliability of a floating gate transistor often used in memory applications by controlling the electric field induced across the tunnel oxide region of the floating gate when discharging electrons from the floating gate. The method comprises the steps of: allowing the active region to ground; and applying a program voltage to the floating gate over a period of time and at a magnitude, by increasing the voltage from zero volts to the magnitude over a first period of at least 1 millisecond (ms.), maintaining the voltage at the magnitude for a second period of around 10 ms.-100 ms. sufficient to place charge on the floating gate, and decreasing the voltage from the magnitude during a third period to zero volts in not greater than 50 microseconds.

Abstract: An output circuit for a semiconductor memory device includes an output buffer for buffering an externally applied output enable signal and a signal outputted from a sense amplifier in accordance with the output enable signal, and an output driver having a CMOS inverter structure connected between a supply voltage and a ground voltage. The output driver includes two pairs of MOS transistors, each having a transistor of a different channel size connected in parallel with each other. When the sense amplifier carries out a sensing operation, the larger channel size MOS transistors are driven by a voltage from a feedback output terminal. When the sensing operation is completed, both pairs of MOS transistors are simultaneously driven in accordance with an output signal of the output buffer. The circuit increases a data signal output speed and decreases the output noise, by turning the data output signal into a completely tri-stated signal during a sensing operation of the sense amplifier.

Abstract: A semiconductor memory device includes gates which open in a data-write operation and a data-read operation to allow a passage of data therethrough, and a control circuit changing an open period of the gates between the data-write operation and the data-read operation.

Abstract: A method and apparatus for programming anti-fuses using a positive voltage switching circuit for connecting an external terminal receiving a positive programming voltage to one plate of an anti-fuse responsive to an active program enable signal. A negative voltage switching circuit connects an external terminal receiving a negative programming voltage to the other plate of the anti-fuse responsive to the active program enable signal. The negative voltage switching circuit normally maintains one plate of the anti-fuse at ground potential when the anti-fuse is not being programmed so that its conductive state can be read by applying a voltage to the other plate of the anti-fuse. The transistors used in the negative voltage switching circuit are fabricated in a well that is isolated from the substrate in which the transistors in the positive voltage switching circuit are fabricated.

Abstract: A memory module has DRAM chips mounted on both a front and a back surface but decoupling capacitors mounted on only the front surface. Each decoupling capacitor is for suppressing current spikes from a pair of DRAM chips. The pair of DRAM chips includes a first DRAM chip on the same surface as the capacitor and a second DRAM chip opposite the first DRAM chip on the back surface of the module. The first DRAM chip belongs to a first bank while the second DRAM chip belongs to a second bank. Two RAS signals are for controlling access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one DRAM chip in the pair of DRAM chips creates a current spike at any time. Thus a capacitor can be shared between the two DRAM chips in the pair. The shared capacitor can be mounted next to or under one of the DRAM chips, or formed within the multi-layer substrate itself.

Abstract: A semiconductor memory circuit designed so as to prevent delay in redundancy access and increase in the chip area due to lengthy wiring between the redundancy control circuit (the redundancy fuse circuits) and the redundancy cell arrays. Redundancy cell arrays 30-32 are placed in a plurality of memory cell arrays 20-23, and the corresponding redundancy fuse circuits 80-82 disposed to make a line with the redundancy word drivers 51-53, respectively. For example, when a defective address is selected 4n redundancy fuse circuit 80, a redundancy judgment signal RDN suspends all the sense amplifier controllers 40, 43 and 44. A redundancy control information RED1 instructs to select a redundancy word driver 51 and the sense amplifier controllers 41 and 42, to select the redundancy cell array 30.

Abstract: The memory device in accordance with the present invention has hierarchical row decoding architecture and comprises at least one main decoder and a plurality of secondary decoders. The decoders have outputs coupled to a plurality of word lines respectively through a plurality of auxiliary lines having first ends respectively connected to said outputs and second ends respectively connected to intermediate points of the word lines.

Abstract: A redundancy circuit and method allows replacement of failed memory cells in a semiconductor memory array. Redundancy true and redundancy not comparator circuits are provided in dynamic logic to selectively enable and disable respective redundant row predecode and normal row predecode circuits. In one embodiment, redundancy circuits are row redundancy circuits. As compared with single static row redundancy comparator circuits which are limited by setup time constraints and which degrade access time irrespective of redundant row utilization, a dual dynamic comparator design reduces access time penalties when redundancy is enabled and eliminates access time penalties when redundancy is not required in a particular semiconductor memory array.

Abstract: A variable sized FIFO buffer whose size changes in accordance with how much data is present to be passed between the two systems is provided.One embodiment of the FIFO buffer includes at least one lower FIFO, at least one upper FIFO, a RAM and a controller. The upper FIFO buffer receives data from a first system and the lower FIFO buffer writes data to a second system. The RAM is utilized when data can no longer flow between the upper and lower FIFO buffers, due to the lower FIFO buffer being temporarily full.

Abstract: A circuit arrangement 10 for driving an MOS field-effect transistor QO allocated to the supply circuit KO of an electrical load R.sub.L contains a charging circuit K1 and a discharging circuit K2, which can be alternatively connected to the MOS field-effect transistor QO. A sensing circuit K3 supplies the measuring signal S.sub.M typical of gate-source voltage U.sub.GS of the MOS field-effect transistor QO, via which the internal resistance of the charging or discharging circuit K1, K2 and/or a current I.sub.a impressed upon these circuits K1, K2, in the sense of a positive feedback, is controlled, in such a way that the resulting time constant, according to which the input capacitance of the MOS field-effect, transistor QO is charged or discharged, becomes smaller during the transition of the MOS field-effect transistor QO from the off state to the conductive state and larger during the transition from the conductive to the off-state.

Abstract: A control circuit of a memory system including a dynamic random access memory may include a first integrated circuit formed on a common substrate. The first integrated circuit may include a circuit responsive to an external memory access request signal for generating a control signal for controlling an operation timing of the dynamic random access memory to supply the control signal to the dynamic random access memory and a circuit for generating an address signal for specifying an address of the dynamic random access memory to be accessed to supply the address signal to the dynamic random access memory. A second integrated circuit includes a read/write circuit for reading data from the dynamic random access memory and for writing data in the dynamic random access memory.