Abstract: A memory device having a hierarchical bit line for decreasing the size of a chip, wherein a global bit line is divided into two parts. Switches are provided for selecting the divided global bit lines and sub-bit lines connected to memory cells that store data in a folded bit line structure.

Abstract: A reference voltage generating circuit and a standby down-converting circuit or a tuning circuit are located in the periphery of the region where a semiconductor device is formed on a semiconductor chip, and a region including an active down-converting circuit which operates during an active cycle or a drive circuit is located adjacent to a circuit actually consuming a current. According to the semiconductor device, increase in area can be suppressed compared to the structure in which both a standby down-converting circuit or drive circuit and the tuning circuit and an active down-converting circuit are located in the vicinity of each current consuming circuit, thereby achieving efficient arrangement of the internal power supply circuitry. As a result, a semiconductor device having efficiently arranged internal power supply circuitry is provided.

Abstract: Systems and methods for steering an optical path to gain access to data locations in a holographic memory cell (HMC). One of the systems includes: (1) a refractive element that receives a complex, spatially-modulated incident beam of light, (2) first and second reflective elements locatable to receive and reflect the incident beam in a Fresnel region thereof and (3) a reflective element steering mechanism, coupled to the first and second reflective elements, that moves the first and second reflective elements in tandem to steer the incident beam with respect to the HMC thereby to cause the incident beam to illuminate a location on the HMC that is a function of a movement of the first and second reflective elements.

Abstract: A method of repairing over-erased flash EPROM cells (10) includes erasing the cells (12) and repairing the cells by a self-converging repair with a control gate bias (14), on a column by column basis. The self-converging repair includes grounding the sources (104) of the cells in a column, applying a pulsed bias voltage to the control gates of the cells (110), and a pulsed positive voltage to the drains of the cells (106). By varying the bias voltage at the control gate, the resulting threshold voltage of the cells after repair can be modulated to be greater than or less than an inherent steady state convergence value. Once one column of cells is repaired, the process is repeated on a subsequent column.

Abstract: A laser beam scanning optical apparatus which has Moire fringes generating elements which is located near a position optically equivalent to a scanning surface and modulates a laser beam emitted from a laser source to generate Moire fringes. The Moire fringes generating elements comprises, for example, a first filter which has spatial grating and a second filter which has spatial grating which slants slightly with respect to the spatial grating of the first filter, the first filter and the second filter being arranged upstream and downstream respectively in an optical path. The laser beam scanning optical apparatus further has a light receiving element for receiving the Moire fringes generated by the Moire fringes generating elements. Focusing means for correcting a position of an image point of the laser beam is driven in accordance with an output of the light receiving element.

Abstract: Following latching of a word line select signal by a latch circuit, a transfer gate is turned off. When a word line is selected, the voltage applied to the latch circuit is shifted to a desired level to apply a desired voltage to the word line from a word line driver. As a result, a predecode signal is applied to a small size buffering circuit to be transmitted to the word line driver at a potential level between Vcc-GND. Therefore, the parasitic capacitance accompanying a predecode signal is reduced.

Abstract: A circuit and a method for detecting the presence of multiple active match lines in a content addressable memory is disclosed. The circuit includes at least one bus group for expressing a unary-encoded address portion of an active match line and, for each match line, an encoding circuit capable of activating a single member of each bus group according to the address of that match line when that match line is active. The multiple match detection circuit advantageously uses the property that each match line has a unique address, and therefore if there is more than one active match line, at least one bus group will have at least two active members. The multiple match detection circuit further comprises, for each bus group, an bus group detection-OR circuit for computing the logical bus group detection-OR of the members of that bus group.

Abstract: A static type semiconductor memory device includes a main bit line pair, and a plurality of memory blocks connected to the main bit line pair. Each of the memory blocks includes a local bit line pair, a static memory connected to the local bit line pair, an amplifier which amplifies potential difference between the paired local bit lines, and a data transfer gate which transfers data between the local bit line pair and the main bit line pair.

Abstract: A circuit for generating memory cell array block selective signals which select memory cell array blocks included in a semiconductor memory device operable in burst mode, wherein the circuit is operated under the control of a burst mode control signal to generate memory cell array block selective signals sequentially and one by one through different and successive time cycles so that, according to the memory cell array block selective signals sequentially generated, the memory cell array blocks are also sequentially selected one by one through the different and successive time cycles for sequentially supplying a word line driver circuit with the memory cell array block selective signals one by one through the different and successive time cycles whereby memory cells included in different memory cell array blocks are sequentially selected one by one through the different and successive time cycles.

Abstract: A process and structure are disclosed for a programmable array for use in a read-only memory comprising diode elements and shorted diode elements. The elements are connected across bit and wordlines. The invention utilizes lateral polysilicon diodes and metal silicide layer bridging the junction of pre-selected diodes to short pre-selected diode elements. Programming is accomplished by either forming the silicide layer across the junctions of pre-selected diodes or removing the silicide layer from the junctions of pre-selected diodes.

Abstract: A wide angle large reflective unobscured system includes a primary reflective element for receiving a broad range of energy, a secondary reflective element for reflecting the energy from the primary reflective element to reimage a virtual entrance pupil at a real aperture stop. A beamsplitter element is provided for reflecting a first portion of the energy, such as visible energy, to a first tertiary reflective mirror, while transmitting a second portion of the energy, such as IR light, to a second tertiary reflector. Each tertiary reflector is capable of focusing the received energies to dual focal planes wherein a compact detector array assembly can convert the images to electronic signals.

Abstract: A PC card is provided through which data can be read and written at a high speed. When a system main unit reads data of one sector from a flash memory of the PC card, the relevant data of one sector from among the data of one block including the relevant data is written in a first RAM, and data of the other sectors is written in a second RAM. Since the system main unit can perform data input/output between it and the high-speed first RAM, the reading and writing speed of data is increased. If the first RAM is contained in a control apparatus and the data is allocated to the first RAM and the second RAM on the basis of the value of the register, it is possible to perform data input/output with ease.

Abstract: Control circuit for producing output voltages from a plurality of sensor signals, wherein each of the sensor signals are identical and mutually phase shifted. The control circuit comprises a plurality of comparators for producing the output voltages, wherein each comparator is respectively supplied with one of the sensor signals and with an amount of hysteresis which depends on the amplitude of one or more of the respective other sensor signals. The control circuit further comprises electronic circuitry for deriving the respective amount of comparator hysteresis for each of the comparators from the amplitude of one or more of the respective other sensor signals.

Abstract: A drive circuit for a semiconductor memory device in which a plurality of memory cell arrays are driven by a divisional decode system, includes a single, row address decoder including a plurality of address latch circuits for holding an address signal for normal operation via a first logic gate unit, and a plurality of normal/redundancy switching circuits for inputting therein held data, and an address signal for redundancy purposes, and for switching the input signal in response to a judging signal for redundancy purposes. The outputs of the switching circuits are activated through a second logic gate unit into which a row address enable signal is inputted. Thus, a driver selection signal during normal operation and a driver selection signal during a redundancy operation are commonly used. As a result, a total number of wiring lines and the number of driver circuits, as well as the chip area, are reduced.

Abstract: A memory-row selector includes an address input terminal, a mode terminal, and even-row-select and odd-row-select terminals. While a test signal level occupies the mode terminal (ie., during a test mode), the selector places either an active level or an inactive level on both of the even-row-select and odd-row-select terminals. An active level on both of the select terminals enables both even-row and odd-row word lines, and allows writing to or reading from memory cells in both odd and even rows. An inactive level on both of the select terminals disables both even-row and odd-row word lines, including the word line coupled to the addressed memory cell.

Abstract: A memory circuit which enables storage of three logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by the state of a tri-state flip-flop. By enabling the current to be detected as positive, negative, or zero, it becomes possible to represent more than one bit of information with the state of the flip-flop.

Abstract: Described is a last stage decoder that generates a local word line signal within a bank of a single-ported memory cell array structure. The decoder inputs predecoded global row address signals, as well as predecoded local row address signals. In order to generate the local word line signal, and thus access a memory cell within a given bank, both one predecoded global row address signal, as well as one predecoded local row address signal must be present. The predecoded local row address signal turns on a pass gate transistor, and allows the predecoded global row address signal to pass through the pass gate transistor and create the local word line signal.

Abstract: A precharge halt access mode system reduces the power consumed during sequential accesses of the memory cells within a memory block. During sequential accesses to the memory cells within a row of the memory block in a synchronous system, the bitlines within the memory are only precharged after the memory access to the last memory cell within the row is complete. After accesses to the other memory cells within the row, the precharging operation of the bitlines within the memory block is halted by a halt precharge logic circuit. Once the memory access to the last column within the memory block is detected the precharging of the bitlines is performed. During sequential accesses to the memory cells within a row in an asynchronous system, the bitlines within the memory block are only precharged during an access to the first memory cell within a row. A wordline disabling circuit will disable a wordline signal after an access to the first memory cell is complete.

Abstract: An optical recording process for recording data on a recording medium of phase-change type employs laser power modulation scheme for mark-length modulation recording. The process selects one of pulse division schemes for modulating the laser power in accordance with a linear velocity on the disc. The recording laser includes m pulses for nT mark having a power level Pw and a duration of .alpha..sub.i T, with m intervals .beta..sub.i T sandwiched therebetween, wherein on condition that m=n-k and .SIGMA..alpha..sub.i +.SIGMA..beta..sub.i =n-j, .alpha..sub.i or bias power Pb.sub.i is changed in accordance with the linear velocity, Pb.sub.i being a bias power level for modulation, k and j being an integer and a real number, respectively, both selected between 0 and 2. A large range of the linear velocity margin can be obtained for the disc without changing either the composition of the phase-change material or multi layer structure on the disc.

Abstract: .?.A circuit comprising a switch series connected to a load; a first and second current recirculating branch alternately connectable parallel to the load, for reducing the current in the same; and a logic control unit for opening and closing the switch and recirculating branches, so that the load is supplied with a current rising to a peak value and then falling rapidly to and oscillating about a lower hold value; a transistor being provided for reducing the voltage supplied to the load by the first recirculating branch at the end of the fast fall phase, so as to eliminate uncontrollable operating zones and prevent the load current from falling below the hold value..!..Iadd.A device for driving an inductive load such as a fuel injector includes a drive switch and a voltage regulator that are coupled to the inductive load. The device also includes a control circuit that is coupled to the voltage regulator, the drive switch, and the inductive load.