Abstract: The memory mat is divided in two banks, which share the sense & latch circuit. As an example of the circuit operation, the information contained in the memory cells in a block of four bit lines BL11a-BL14a connected to a word line WL1a in the memory array MAa of the bank A is temporarily stored in the sense & latch circuits SL11-SL14. The information of bit lines is latched to the sense & latch circuit SLa through the sub-input/output signal lines IO1a and IO2a by the switches YS1a and YS2a that alternately operates at a cycle two times that of the external clock. The latched information is then output onto the input/output signal line IOa by the switch SWa in synchronism with the clock. After the four bit lines BL11a-SB14a have been read out, the sense & latch circuits SL11-S114 in that block are reset and the bit lines on the bank B are precharged while the information on the bank A is being output.

Abstract: A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

Abstract: Power usage of an integrated circuit including an embedded memory array is reduced significantly by preventing a clock signal from clocking unaccessed memory blocks in the embedded memory array while allowing the clock signal to clock the currently accessed memory block. In an exemplary embodiment, the clock signal is gated with individual memory block enable signals such that the clock signal clocks only the currently enabled or accessed memory block. Only one memory block or a limited number of memory blocks out of an array of memory blocks on a data bus is clocked or operated at any one time. In another embodiment, a delay circuit delays the removal of the clock signal to the accessed memory block until a period of time after the enable signal to the memory block is removed. Thus, the accessed or enabled memory block is allowed to clock internally substantially only during a time corresponding to when that memory block is enabled or accessed.

Abstract: In a semiconductor memory storing multivalue information, a sense section includes a first latch receiving an output of a first differential amplifier in a sense amplifier, a second latch receiving an output of a second differential amplifier in the sense amplifier and an output of the first latch, and a third latch receiving an output of a third differential amplifier in the sense amplifier and an output of the second latch. When a selected memory cell has the lowest threshold, the output of the first latch becomes a low level, and correspondingly, the output of the second latch is forcibly brought to the low level in response to the low level of the output of the first latch, and then, the output of the third latch is forcibly brought to the low level in response to the low level of the output of the second latch.

Abstract: A high density EEPROM cell array structure utilizes a floating gate architecture for the access transistor and a double poly process in which the control gate and floating gate of both the access transistor and the memory cell are self-aligned, resulting in a much more compact cell than previously available. In addition, the process flow utilizes only two masks compared to the four mask flow utilized in the prior art. This leads to cost reduction in the fabrication process. The structure results in significantly reduced read time for the cell array.

Abstract: The frequency of a clocking signal is adjusted in response to fluctuations in the power supply voltage. In one embodiment, a control circuit has a plurality of clock input terminals each coupled between selected adjacent ones of the stages of a multiple-stage ring oscillator circuit and has an output clock terminal coupled to an input terminal of the ring oscillator circuit. In this manner, the control circuit may implement a plurality of loops each including a different variety of the stages of the ring oscillator circuit, wherein the clocking signal associated with each of the loops has a unique frequency. A plurality of trip voltages each being equal to a unique predetermined fraction of the power supply voltage are compared to a reference voltage. The control circuit selects, in response to the comparison of the trip voltages and the reference voltage, one of the loops mentioned above to provide its clocking signal to an output terminal of the oscillator.

Abstract: Disclosed is a method for amplifying a data signal read from a memory device. The method includes sensing an initial voltage difference across a data bus that is coupled to the memory device. Producing an initial voltage difference across a sensed data bus after the sensing detects the initial voltage difference. The initial voltage difference is configured to partially separate a pair of nodes associated with the sensed data bus. The method further includes subsequently isolating the data bus from the sensed data bus to rapidly further separate the pair of nodes associated with the sensed data bus, the rapid separation producing the amplified data signal across the sensed data bus.

Abstract: A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed in both coordinate directions; its symmetry makes the Dual-addressed Rectifier Storage (DRS) Array very scaleable, particularly when made as an integrated circuit. For even greater storage flexibility, multiple digital rectifier storage arrays can be incorporated into the device, one or more of which can be made removable and interchangeable.

Abstract: An apparatus for minimizing vibration of images in video cameras due to vibration of the operator's hands includes a motion detector, an electric field generator which receives information from the motion detector and generate voltages related to the horizontal and vertical motions, and a hand vibration corrector which uses the voltages from the electric field generator to control the refractive index of a medium through which the incoming video images are passing, to thereby adjust the position of the incoming images. A CCD converts the optical signals of the hand vibration correcting means into electrical signals. The refractive index of the crystal having the electro-optical effect is controlled by electrical signals and the optical source of the input images is optically corrected. Consequently, a high speed response and high precision controlled resolution are provided. Further, the apparatus has a simple structure, and therefore, it can greatly contribute to the camera image stabilization.

Abstract: A frequency switching circuit is controlled by a low address strobe signal XRAS. A sub-boosted power supply generating circuit is driven at a low frequency generated by a first oscillating circuit during the standby of a DRAM, and at a high frequency generated by a second oscillating circuit during the operation of the DRAM. The sub-boosted power supply generating circuit is driven in a shorter cycle during the operation than during the standby. Consequently, charges are supplied to a booster power source to boost the voltage level thereof. Accordingly, even if the period of the operation state is increased, a drop in voltage level of the boosted power supply caused by a transistor off leak current and a junction leak current can be controlled. Thus, the malfunction of a circuit can be prevented from occurring due to the drop in voltage level of the boosted power supply.

Abstract: Method and apparatus for imaging an object illuminated with light onto a photodetector array including a microcomputer for controlling the light gathering of the photodetector array by varying the amount of light reflected onto the photodetector array and by varying a photodetector array variable in response to the output of the photodetector array. In one embodiment, the amount of light reflected onto the photodetector array is varied by modifying either the time the light is reflected onto the array or the power of the light reflected onto the array.

Abstract: Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor that provides easy and firm grasping for insertion and removal. The digital media devices of the family have respective body portions (312, 322, 332, 342, 352 and 362) preferably of a rigid or semi-rigid material. Preferably, the digital media devices of the family use serial memory requiring few power and signal lines, so that few electrical contacts are required.

Abstract: A memory system having a single-sided memory cell, a first voltage supply terminal and a control circuit is provided. The single-sided memory cell has a first node and a second node. Data values are written to the memory cell by selectively applying data signals to the first node or the second node, and data values are read from the memory cell from the second node. The control circuit is coupled to receive a data signal having one of a first state and a second state. The control circuit couples the first node of the memory cell to the first voltage supply terminal when the data signal is in the first state, thereby writing a first data value to the memory cell. The control circuit couples the second node of the memory cell to the first voltage supply terminal when the data signal is in the second state, thereby writing a second data value to the memory cell.

Abstract: In a timer apparatus, the clock controlling circuit thereof outputs a clock signal during a period in which an input signal is significant. The counter thereof counts the number of pulses of the clock signal to generate a count-up signal when the value of count reaches a prescribed value. The initialization circuit thereof outputs an initialization signal when the input is not significant. The clock controlling circuit stops the output of the clock signal when the count-up signal is generated. Thereby, it is prevented to misjudge the detection of an effective pulse width to achieve the effective pulse width though the pulse width of the pulse does not actually reach the effective pulse width actually.

Abstract: A memory array circuit has a matrix of column lines and row lines. A plurality of non-volatile storage capacitors, each having a floating gate for the storage of charges, are arranged in the matrix. Each storage capacitor has a data node and a voltage node, with a floating gate therebetween. Each of the plurality of non-volatile storage capacitors has an associated column line and an associated row line, with the voltage node connected to the associated row line. A diode connects the data node of a storage capacitor to its associated column line. A first decoder decodes a first address signal and selects one of the column lines. A second decoder decodes a second address signal, and generates a row output signal, with each row output signal of the second decoder having a corresponding row line.

Abstract: Apparatus, and an associated method, for calibrating a device responsive to values of a reference signal. The reference signal may be subject to short-term disturbances. In one implementation, a cellular radio base station utilizes a Stratum-2 oscillator to which to phase-lock a base station VCO. Compensation is made for the aging of the Stratum-2 oscillator, thereby to provide a regulation signal causing the VCO to exhibit acceptable short-term and long-term frequency stability characteristics.

Abstract: A high reliability logic circuit designed to withstand a single event upset (SEU) induced by an ion transitioning through a semiconductor structure is embodied in a memory circuit which includes a first memory cell and a second memory cell. The first and second memory cells receive a first input signal and a second input signal. The memory cells contain a logic circuit for producing a logic signal output driven by either a pullup or pulldown driver when the first and second input signals are of a desired logic state and produces a high impedance output if either input signal is not of their respective desired logic states.The memory cells also have sufficient nodal capacitance such that the output from the first or second memory cell will not be corrupted by an SEU in the logic circuit of either the first or second memory cell.The outputs of the first memory cell and second memory cell are further summed in analog fashion to produce a single output from the memory circuit.

Abstract: This invention relates to a compact wide-angle lens which consists of five members. The first member and the last member are each divergent lenses of low deviation, which consist of low refractivity crown glass. The second member and the third member are convergent lenses made of high refractivity crown glass. The fourth member, which is the final member of the lens according to the invention, consists of a convergent lens and a divergent lens which are cemented to each other. Type of glass are used for this cemented member which have a very low difference in refractive index but a very high difference in dispersion. The convergent lens has a low dispersion and the divergent lens has a high dispersion. One of the two glass/air surfaces of the cemented member is aspherical. A lens such as this according to the invention has a maximum aperture ratio of at least 1:5.6 and an image angle of 105.degree.. The chromatic correction is well defined and is very substantially independent of the distance of the object.

Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Abstract: This invention relates to a test pattern structure comprising a test pattern structure for endurance test of a flash memory device comprising: at least three active regions formed on a semiconductor substrate, each active region being isolated by a field oxide film; a common drain region formed on each active region, respectively; source regions formed on left and right sides of the common drain region in each active region, respectively; a first common floating gate formed along left side of each common drain region; a second common floating gate formed along right side of each common drain region; a control gate overlapped with the first and second floating gates, respectively and connected from each other at both ends of the first and second floating gates; a select gate formed over the common drain region, the source regions and the control gate in each active region, respectively; and metal wires connected to the common drain region, the source regions and the control gate in each active region, respecti