Patents Examined by David Chen
  • Patent number: 10453928
    Abstract: According to one example embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby reducing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: October 22, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventor: Raymond A. Kjar
  • Patent number: 10438892
    Abstract: A semiconductor device according to present embodiment has first wirings provided in a first area and made of a first metal. A first gap is provided between the first wirings adjacent to each other. Second wirings or contact plugs are provided in a second area in which the first wirings are not provided. The second wirings or contact plugs are made of a second metal. A first insulation film is provided between the second wirings or contact plugs adjacent to each other. The first insulation film has second gaps. A second insulation film is provided on the first wirings, the first gap, and the second gaps.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: October 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Toshiyuki Morita
  • Patent number: 10431501
    Abstract: Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes forming an interlayer dielectric layer on a base substrate; forming a plurality of first openings and second openings in the interlayer dielectric layer, one first opening connecting to a second opening, the one first opening being between the second opening and the base substrate; forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings; forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer; forming an amorphous silicon layer on the cap layer at least on the bottoms of the first openings; performing a thermal annealing process on the amorphous silicon layer, the cap layer and the high-K dielectric; removing the amorphous silicon layer; and forming a metal layer, in the first openings and the second openings.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: October 1, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10424565
    Abstract: A semiconductor chip, an optoelectronic device including a semiconductor chip, and a method for producing a semiconductor chip are disclosed. In an embodiment the chip includes a semiconductor body with a first main surface and a second main surface arranged opposite to the first main surface, wherein the semiconductor body includes a p-doped sub-region, which forms part of the first main surface, and an n-doped sub-region, which forms part of the second main surface and a metallic contact element that extends from the first main surface to the second main surface and that is electrically isolated from one of the sub-regions.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: September 24, 2019
    Assignee: OSRAM Opto Semiconductor GmbH
    Inventors: Andreas Weimar, Frank Singer, Anna Kasprzak-Zablocka, Sabine vom Dorp
  • Patent number: 10411168
    Abstract: An optoelectronic semiconductor component includes a semiconductor chip having a semiconductor layer sequence including an active region that generates radiation; a radiation exit surface running parallel to the active region; a mounting side surface that fixes the semiconductor component and runs obliquely or perpendicularly to the radiation exit surface and at which at least one contact area for external electrical contacting is accessible; a molded body molded onto the semiconductor chip in places and forming the mounting side surface at least in regions; and a contact track arranged on the molded body and electrically conductively connecting the semiconductor chip to the at least one contact area.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: September 10, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Joachim Reill, Frank Singer, Norwin von Malm, Matthias Sabathil
  • Patent number: 10388698
    Abstract: A resistive memory includes a semiconductor substrate, a dielectric layer, an insulating layer and a metal electrode layer. The semiconductor substrate has a top surface and a recess extending downwards into the semiconductor substrate from the top surface. The dielectric layer is disposed on the semiconductor substrate and has a first through-hole aligning the recess. The insulating layer is disposed in the first through-hole and the recess. The metal electrode layer is disposed on the insulating layer by which the metal electrode layer is isolated from the semiconductor substrate.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: August 20, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Hao Tseng, Dai-Ying Lee, Erh-Kun Lai
  • Patent number: 10381516
    Abstract: A semiconductor light emitting device which includes at least one concave on a light extraction surface opposite to a surface on which a semiconductor stack comprising a light emitting layer between a n-type semiconductor layer and a p-type semiconductor layer is mounted. The concave has not less than two slopes each having a different slope angle in a direction that a diameter of the concave becomes narrower toward a bottom of the concave from an opening of the concave and a slope having a gentle slope angle is provided with irregularities and a slope having a steep slope angle is a flat surface.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: August 13, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Yohei Wakai, Masahiko Onishi
  • Patent number: 10381373
    Abstract: A method of forming a three-dimensional memory device includes forming at the least one lower level dielectric layer over a semiconductor substrate, forming a buried source line over the least one lower level dielectric layer and over the semiconductor substrate, such that the buried source line is electrically connected to the semiconductor substrate, forming an alternating stack of insulating layers and sacrificial material layers over the buried source line, such that the sacrificial material layers are subsequently replaced with, electrically conductive layers, forming memory openings through the alternating stack by etching through the alternating stack after the buried source line is electrically connected to the semiconductor substrate, and forming memory stack structures in the memory openings. Each memory stack structure includes a vertical semiconductor channel electrically connected to the buried source line and a memory film laterally surrounding the vertical semiconductor channel.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yasuchika Okizumi, Michiru Hirayama, Naoto Norizuki, Satoshi Shimizu, Yasuo Kasagi, Kimiaki Naruse
  • Patent number: 10374068
    Abstract: Tunnel field effect devices and methods of fabricating tunnel field effect devices are described. In one embodiment, the semiconductor device includes a first drain region of a first conductivity type disposed in a first region of a substrate, a first source region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type, a first channel region electrically coupled between the first source region and the first drain region, the first source region underlying a least a portion of the first channel region, and a first gate stack overlying the first channel region.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: August 6, 2019
    Assignees: INFINEON TECHNOLOGIES AG, INDIAN INSTITUTE OF TECHNOLOGY BOMBAY
    Inventors: Harald Gossner, Ramgopal Rao, Ram Asra
  • Patent number: 10361240
    Abstract: This invention relates to an X-ray sensor having flexible properties and to a method of manufacturing the same. This X-ray sensor includes an array substrate including a semiconductor layer having a light-receiving element; a scintillator panel bonded to the array substrate and including a scintillator layer; a first polymer layer attached to an outer surface of the array substrate by a first adhesive layer; a second polymer layer attached to an outer surface of the scintillator panel by a second adhesive layer; and a third adhesive layer disposed between the array substrate and the scintillator panel so as to attach the array substrate and the scintillator panel to each other.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: July 23, 2019
    Assignees: Rayence Co., Ltd., VATECH EWOO Holdings Co., Ltd.
    Inventors: Sung Kyn Heo, Ho Seok Lee
  • Patent number: 10355108
    Abstract: An exemplary method of forming a fin field effect transistor that includes first and second etching processes to form a fin structure. The fin structure includes an upper portion and a lower portion separated at a transition. The upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate. The lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng Yuan, Hung-Ming Chen, Tsung-Lin Lee, Chang-Yun Chang, Clement Hsingjen Wann
  • Patent number: 10347580
    Abstract: A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: July 9, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Matthias Stecher
  • Patent number: 10340451
    Abstract: In switching elements each using a two-terminal-type variable resistance element, improper writing or any improper operation is often caused and the reliability of the switching elements cannot be improved easily. A switching element according to the present invention is equipped with a first variable resistance element equipped with a first input/output terminal and a first connection terminal, a second variable resistance element equipped with a second input/output terminal and a second connection terminal, and a rectifying element equipped with a control terminal and a third connection terminal, wherein the first connection terminal, the second connection terminal and the third connection terminal are connected to one another.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: July 2, 2019
    Assignee: NEC CORPORATION
    Inventors: Munehiro Tada, Toshitsugu Sakamoto, Naoki Banno, Koichiro Okamoto
  • Patent number: 10332882
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided in the present disclosure. The semiconductor device includes a substrate including a first active region and a second active region divided by a shallow trench isolation (STI) region, a protective structure located on the STI region, a first semiconductor structure on the first active region, and a second semiconductor structure on the second active region of the substrate including a high-k dielectric layer and a metal gate layer over the high-k dielectric layer. The method for fabricating the semiconductor device is a process of the high-k dielectric layer deposited before the formation of the first and second semiconductor structures.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry Hak-Lay Chuang, Wei-Cheng Wu
  • Patent number: 10325937
    Abstract: The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate. A thin film transistor substrate includes a substrate; a first thin film transistor disposed on the substrate, the first thin film transistor including a poly crystalline semiconductor layer, a first gate electrode over the poly crystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor disposed on the substrate, the second thin film transistor including a second gate electrode, an oxide semiconductor layer over the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed over the first gate electrode and the second gate electrode and under the oxide semiconductor layer.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: June 18, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Youngjang Lee, Kyungmo Son, Sohyung Lee, Moonho Park, Sungjin Lee
  • Patent number: 10297601
    Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Bum Kim, Myung-Gil Kang, Kang-Hun Moon, Cho-Eun Lee, Su-Jin Jung, Min-Hee Choi, Yang Xu, Dong-Suk Shin, Kwan-Heum Lee, Hoi-Sung Chung
  • Patent number: 10274799
    Abstract: An array substrate and a fabrication method thereof, a test method and a display device are provided. The array substrate comprises a plurality of pixel units formed on a base substrate, a thin film transistor (TFT) and a pixel electrode, a passivation layer, and a common electrode sequentially formed on the base substrate being provided in the pixel unit, the pixel electrode being connected with a drain electrode of the thin film transistor (TFT), wherein, a via hole located above the pixel electrode is further provided in the at least one of the pixel units, the via hole penetrates through the common electrode and the passivation layer, and a bottom of the via hole is in contact with a conductive surface (S, S?), and the conductive surface (S, S?) is electrically connected with a portion of the pixel electrode.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: April 30, 2019
    Assignees: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventor: Shiqiang Huang
  • Patent number: 10269938
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin structure over the base. The fin structure has sidewalls. The semiconductor device structure includes a passivation layer over the sidewalls. The passivation layer includes dopants. The dopants include at least one element selected from group 4A elements, and the dopants and the substrate are made of different materials. The semiconductor device structure includes an isolation layer over the base and surrounding the fin structure and the passivation layer. A first upper portion of the fin structure and a second upper portion of the passivation layer protrude from the isolation layer. The semiconductor device structure includes a gate electrode over the first upper portion of the fin structure and the second upper portion of the passivation layer.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Chin Hsu, Yi-Wei Chiu, Wen-Zhong Ho, Tzu-Chan Weng
  • Patent number: 10263013
    Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony K. Stamper, Steven M. Shank, Siva P. Adusumilli
  • Patent number: 10205056
    Abstract: A light emitting diode includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, a second electrode, a static electrode and a carbon nanotube structure. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked on the substrate. The first electrode is located on and electrically connected to the first semiconductor layer. The carbon nanotube structure is located on and electrically connected to the second semiconductor layer. The second electrode is located on and electrically connected to the carbon nanotube structure. The static electrode is located between the second semiconductor layer and the carbon nanotube structure. The carbon nanotube structure includes a first portion in direct contact with the second semiconductor layer and a second portion sandwiched between the static electrode and the second electrode.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: February 12, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Qun-Qing Li, Kai-Li Jiang, Shou-Shan Fan