Patents Examined by David E. Graybill
  • Patent number: 10930843
    Abstract: A method of fabricating a magnetic storage device includes depositing a first conductive material. The method further includes electrically isolating distinct instances of the first conductive material to form a first wire extending along a first direction. The method further includes depositing, on the distinct instances of the first conductive material, a set of device layers. The method further includes electrically isolating distinct instances of the device layers to form spin orbit torque magnetic random access memory (SOT-MRAM) devices positioned on distinct instances of the first conductive material. The method further includes depositing, on the distinct instances of the device layers, a layer of a second conductive material and electrically isolating a plurality of distinct instances of the layer of the second conductive material to form a plurality of second wires extending along a second direction. The second direction is different from the first direction.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: February 23, 2021
    Assignee: SPIN MEMORY, INC.
    Inventor: Satoru Araki
  • Patent number: 10910475
    Abstract: A method of manufacturing a silicon wafer includes extracting an n-type silicon ingot over an extraction time period from a silicon melt comprising n-type dopants, adding p-type dopants to the silicon melt over at least part of the extraction time period, so as to compensate an n-type doping in the n-type silicon ingot by 20% to 80%, and slicing the silicon ingot.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: February 2, 2021
    Assignee: Infineon Technologies AG
    Inventors: Nico Caspary, Hans-Joachim Schulze
  • Patent number: 10910217
    Abstract: By sequentially performing, a plurality of times, a step of supplying a mixed gas of an organic metal-containing source gas and an inert gas to a process chamber housing a substrate by adjusting a flow velocity of the mixed gas on the substrate to 7.8 m/s to 15.6 m/s and adjusting a partial pressure of the organic metal-containing source gas in the mixed gas to 0.167 to 0.3, a step of exhausting the process chamber, a step of supplying an oxygen-containing gas to the process chamber, and a step of exhausting the process chamber, a metal oxide film is formed on the substrate.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: February 2, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshimasa Nagatomi, Hirohisa Yamazaki
  • Patent number: 10908465
    Abstract: An array substrate is provided, comprising a display area and a non-display area outside the display area. The non-display area is provided with a first transistor and a first conductive region electrically connected with the first transistor. A control terminal, and one of a source and a drain of the first transistor are both electrically connected to a data line in the display area, the other of the source and the drain of the first transistor is electrically connected to the first conductive region. For this array substrate, the static electricity generated on the data line in the rubbing process can be led to the first conductive region through the first transistor, so as to prevent the static electricity from being transmitted to the display area, which could have destroyed the TFT device in the display area.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: February 2, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Peng Zeng, Yonggang Du, Zhangfei Gao, Guohua Xu
  • Patent number: 10886383
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Byron Ho, Steven Jaloviar, Jeffrey S. Leib, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10886429
    Abstract: The invention relates to a method of manufacturing an optoelectronic device (1) produced on the basis of GaN, comprising an emission structure (10) configured to emit a first light radiation at the first wavelength (?1), the method comprising the following steps: i. producing a growth structure (20) comprising a nucleation layer (23) of Inx2Ga1-x2N at least partially relaxed; ii. producing a conversion structure (30), comprising an emission layer (33) configured to emit light at a second wavelength (?2), and an absorption layer (34) produced on the basis of InGaN; iii. transfer of the conversion structure (30) onto the emission structure (10) in such a way that the absorption layer (34) is located between the emission structure (10) and the emission layer (33) of the conversion structure.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: January 5, 2021
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, THALES
    Inventors: Amelie Dussaigne, Ivan-Christophe Robin
  • Patent number: 10854720
    Abstract: A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a p-type doped layer, a gate electrode, a passivation layer, and a field plate. The active layer is disposed on the substrate. The source electrode, the drain electrode and the p-type doped layer are disposed on the active layer. The p-type doped layer is disposed between the source electrode and the drain electrode, and has a first thickness. The gate electrode is disposed on the p-type doped layer. The passivation layer covers the gate electrode and the active layer. The field plate is disposed on the passivation layer and is electrically connected to the source electrode. The field plate includes a field dispersion portion disposed between the gate electrode and the drain electrode. The passivation layer between the field dispersion portion and the active layer has a second thickness smaller than the first thickness.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: December 1, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Wen-Chia Liao
  • Patent number: 10854732
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Jeffrey S. Leib, Jenny Hu, Anindya Dasgupta, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10847580
    Abstract: Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including elevated temperatures associated with a read or write operation of a neighboring cell, corrupting the data stored in them. To prevent this thermal disturb effect, memory cells may be separated from one another by thermally insulating regions that include one or several interfaces. The interfaces may be formed by layering different materials upon one another or adjusting the deposition parameters of a material during formation. The layers may be created with planar thin-film deposition techniques, for example.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Paolo Fantini
  • Patent number: 10811284
    Abstract: A substrate processing method which can clean a peripheral portion of a substrate after polishing and can check the cleaning effect of the peripheral portion of the substrate is disclosed. The substrate processing method includes polishing a peripheral portion of the substrate by pressing a polishing tape having abrasive grains against the peripheral portion of the substrate with a first head, cleaning the peripheral portion of the substrate by supplying a cleaning liquid to the peripheral portion of the substrate after polishing, bringing a tape having no abrasive grains into contact with the peripheral portion of the substrate after cleaning by a second head, applying light to the tape and receiving reflected light from the tape by a sensor, and judging that the peripheral portion of the substrate is contaminated when an intensity of the received reflected light is lower than a predetermined value.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 20, 2020
    Assignee: EBARA CORPORATION
    Inventors: Toshifumi Watanabe, Satoru Yamamoto, Yu Machida
  • Patent number: 10804164
    Abstract: To improve reliability of a semiconductor device, in a method of manufacturing the semiconductor device, a ground plane region of an n-type MISFET is formed by ion-implanting a p-type impurity and nitrogen (N) and a ground plane region of a p-type MISFET is formed by ion-implanting an n-type impurity and one of carbon (C) and fluorine (F).
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 13, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Keiichi Maekawa
  • Patent number: 10797115
    Abstract: The display panel includes a light emitting device, three quantum dot converters including quantum dot particles and converting light of a first color emitted from the light emitting device to light of a different color and emitting the light of the different color, a transmission part transmitting light of the first color emitted from the light emitting device, and a transparent substrate disposed on one side of the three quantum dot converters and the transmission part. One of the three quantum dot converters emits a white light to the transparent substrate.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kye Hoon Lee
  • Patent number: 10790378
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Byron Ho, Steven Jaloviar, Jeffrey S. Leib, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10784418
    Abstract: A vertical type light emitting element is disclosed. The vertical type light emitting element includes: a color conversion electrode part including a first electrode pad and a color conversion layer; a reflective electrode part including a second electrode pad and a reflective layer; and a light emitting semiconductor part interposed between the color conversion electrode part and the reflective electrode part. The color conversion electrode part further includes an electrically conductive light transmissive plate. The first electrode pad and the color conversion layer are interposed between the light transmissive plate and the upper surface of the light emitting semiconductor part. Roughnesses are formed on the upper surface of the light emitting semiconductor part bordering the color conversion electrode part to increase the amount of light entering the color conversion electrode part through the light emitting semiconductor part.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 22, 2020
    Assignee: LUMENS CO., LTD.
    Inventors: Taekyung Yoo, Daewon Kim
  • Patent number: 10784200
    Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Ian D. Melville, Kevin S. Petrarca, Kenneth P. Rodbell
  • Patent number: 10777413
    Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yuping Ren, Guoxiang Ning, Haigou Huang, Sunil K. Singh
  • Patent number: 10777672
    Abstract: Embodiments of this disclosure are directed to a multi-gate gallium nitride (GaN) transistor and methods of making the same. The multi-gate GaN transistor includes a gallium nitride layer. The GaN transistor includes two or more gate electrodes between a drain electrode and a source electrode. A polarization layer is located between the first gate electrode and the second gate electrode, the polarization layer forming a two dimensional electron gas (2DEG) within the GaN layer, the 2DEG electrically coupling the first gate electrode and the second gate electrode.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Patent number: 10777417
    Abstract: A dressing device including: a disk that has an opening on an inside, the disk dressing a polishing surface for polishing a substrate; a rotatable holder, the disk being coupled to a lower surface side of the holder, the holder being provided with a first flow passage that passes from a lower surface to an upper surface, the lower surface being inside an outer edge of the opening of the disk; and a housing that is provided with a distance from the upper surface of the holder, the housing being provided with a second flow passage in an interior, the housing being fixed such that an opening of the second flow passage faces the upper surface of the holder, the second flow passage being connected with a supply source and a suction source of process liquid.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: September 15, 2020
    Assignee: EBARA CORPORATION
    Inventor: Hiroyuki Shinozaki
  • Patent number: 10763364
    Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: September 1, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Kern Rim, Da Yang, Peijie Feng
  • Patent number: 10741469
    Abstract: The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 11, 2020
    Assignee: MEDIATEK INC.
    Inventors: Hsien-Hsin Lin, Ming-Tzong Yang, Wen-Kai Wan