Patents Examined by David E. Graybill
  • Patent number: 10388552
    Abstract: Apparatus, systems, and processes for substrate breakage detection in a thermal processing system are provided. In one example implementation, a process can include: accessing data indicative of a plurality of temperature measurements for a substrate, the plurality of measurements obtained during a cool down period of a thermal process; estimating one or more metrics associated with a cooling model based at least in part on the data indicative of the plurality of temperature measurements; and determining a breakage detection signal based at least in part on the one or more metrics associated with the cooling model. The breakage detection signal is indicative of whether the substrate has broken during thermal processing.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: August 20, 2019
    Assignee: Mattson Technology, Inc.
    Inventor: Joseph Cibere
  • Patent number: 10381222
    Abstract: A substrate treatment method of performing a plurality of predetermined treatments on a substrate to form a plurality of patterns stacked on the substrate, the substrate treatment method includes: a calculation step of calculating, about patterns in two layers stacked on the substrate, a mutual pattern displacement amount being a displacement amount between the patterns in the two layers, based on an end portion positional displacement of a pattern in an upper layer, an end portion positional displacement of a pattern in a lower layer, and an overlay of the patterns in the two layers; and a correction step of correcting, when the mutual pattern displacement amount exceeds a predetermined threshold, treatment conditions in the predetermined treatments to make the mutual pattern displacement amount fall within the predetermined threshold.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: August 13, 2019
    Assignee: Tokyo Electron Limited
    Inventor: Shinji Kobayashi
  • Patent number: 10355229
    Abstract: The present invention generally relates to nanoscale wires and tissue engineering. Systems and methods are provided in various embodiments for preparing cell scaffolds that can be used for growing cells or tissues, where the cell scaffolds comprise nanoscale wires. In some cases, the nanoscale wires can be connected to electronic circuits extending externally of the cell scaffold. Such cell scaffolds can be used to grow cells or tissues which can be determined and/or controlled at very high resolutions, due to the presence of the nanoscale wires, and such cell scaffolds will find use in a wide variety of novel applications, including applications in tissue engineering, prosthetics, pacemakers, implants, or the like. This approach thus allows for the creation of fundamentally new types of functionalized cells and tissues, due to the high degree of electronic control offered by the nanoscale wires and electronic circuits.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: July 16, 2019
    Assignee: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Bozhi Tian, Jia Liu
  • Patent number: 10354990
    Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: July 16, 2019
    Assignee: Alpha and Omega Semiconductor incorporated
    Inventor: Madhur Bobde
  • Patent number: 10340137
    Abstract: A method of forming a thin film is described. The method includes treating at least a portion of a surface exposed on a substrate with an adsorption-promoting agent to alter a functionality of the exposed surface and cause subsequent adsorption of an organic precursor, and thereafter, adsorbing the organic precursor to the functionalized surface to form a carbon-containing film. Then, at least a portion of the surface of the carbon-containing film is exposed to an ion flux to mix the adsorbed carbon-containing film with the material of the underlying substrate and form a mixed film.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: July 2, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Peter Ventzek, Alok Ranjan
  • Patent number: 10332881
    Abstract: Integrating a gate-all-around (GAA) field-effect transistor(s) and a FinFET(s) on a common substrate of a semiconductor die is disclosed. GAA FETs and FinFETs can form integrated circuits (ICs). GAA FETs and FinFETs are integrated on a common substrate to optimize advantages of each type of FET. For example, FinFETs may be formed in the common substrate in the semiconductor die for forming circuits where reduced resistance and capacitance are important for performance, whereas GAA FETs may be formed in the common substrate in the semiconductor die for forming circuits with decreased threshold voltage to allow voltage scaling to lower supply voltages to reduce power consumption and also to reduce silicon area as a result of vertically stacked devices. This supports a designer having the freedom to separate control the channel width of the GAA FETs and FinFETs, which may be important for controlling drive strength and/or area for different circuits.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 25, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Mustafa Badaroglu, Kern Rim
  • Patent number: 10312137
    Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming a hardmask layer that may be utilized to transfer patterns or features to a film stack with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked semiconductor devices. In one embodiment, a method of forming a hardmask layer on a substrate includes forming a seed layer comprising boron on a film stack disposed on a substrate by supplying a seed layer gas mixture in a processing chamber, forming a transition layer comprising born and tungsten on the seed layer by supplying a transition layer gas mixture in the processing chamber, and forming a bulk hardmask layer on the transition layer by supplying a main deposition gas mixture in the processing chamber.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: June 4, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Eswaranand Venkatasubramanian, Susmit Singha Roy, Pramit Manna, Abhijit Basu Mallick
  • Patent number: 10312055
    Abstract: A method of forming a film on a substrate by PEALD includes deposition cycles, each including (i) feeding a precursor in a pulse to a reaction space to adsorb a precursor on a surface of a substrate; (ii) after step (i), applying RF power to a second electrode to generate in the reaction space a plasma to which the precursor-adsorbed surface is exposed, thereby forming a sublayer on the surface; and (iii) applying a bias voltage to the second electrode while applying RF power in step (ii), which bias voltage is negative with reference to a potential on a surface of the first electrode, wherein the cycle is repeated to deposit multiple sublayers until a film constituted by the sublayers has a desired thickness.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: June 4, 2019
    Assignee: ASM IP Holding B.V.
    Inventor: Toshiya Suzuki
  • Patent number: 10304940
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Tahir Ghani, Byron Ho, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10304685
    Abstract: A manufacturing method of an integrated circuit includes following steps. A dummy gate with a first mask structure formed thereon and a semiconductor gate with a second mask structure formed thereon are formed on a substrate. A top surface of the semiconductor gate is lower than a top surface of the dummy gate. A first removing process is performed to remove the first mask structure and a part of the second mask structure. A dielectric layer is formed covering the dummy gate, the semiconductor gate, and the second mask structure. A second removing process is performed to remove the dielectric layer above the dummy gate. The dummy gate is removed for forming a trench. A metal gate structure is formed in the trench. The semiconductor gate is covered by the second mask structure during the second removing process and the step of removing the dummy gate.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: May 28, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chao-Sheng Cheng
  • Patent number: 10297574
    Abstract: There is provided a semiconductor device assembly with an interposer and method of manufacturing the same. More specifically, in one embodiment, there is provided a semiconductor device assembly comprising a semiconductor substrate, at least one semiconductor die attached to the semiconductor substrate, an interposer disposed on the semiconductor die, and a controller attached to the interposer. There is also provided a method of manufacturing comprising forming a first subassembly by coupling a substrate and a semiconductor die, and forming second subassembly by attaching a controller to an interposer, and coupling the first subassembly to the second subassembly.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: May 21, 2019
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Matt Schwab
  • Patent number: 10290496
    Abstract: A substrate processing apparatus includes: a protrusion portion formed by a side peripheral wall of a processing container which swells outward, and configured to form a vertically elongated space communicating with a processing space for accommodating a substrate holder and performing a process; a gas discharge portion provided in the vertically elongated space, and configured to discharge a process gas into the processing space; an antenna provided in the protrusion portion along a vertical direction and supplied with a high-frequency power for converting the process gas into a plasma in the vertically elongated space; and a shield extending leftward and rightward in the protrusion portion at positions closer to the processing space than the antenna and configured to shield an electric field formed by the antenna and to suppress a formation of the plasma in the processing space.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: May 14, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jun Ogawa, Kazuo Yabe
  • Patent number: 10290997
    Abstract: A method of producing an electronic component includes providing a surface comprising a first region and a second region adjoining the first region, arranging a sacrificial layer above the first region of the surface, arranging a passivation layer above the sacrificial layer and the second region of the surface, creating an opening in the passivation layer above the first region of the surface, wherein the opening in the passivation layer is created with an opening area that is smaller than the first region, and removing the sacrificial layer and the portions of the passivation layer that are arranged above the first region.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: May 14, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Jens Mueller, Christoph Stephan, Robert Walter, Stefan Hartauer, Christian Rumbolz
  • Patent number: 10283709
    Abstract: In an embodiment, a substrate that includes a cell region and a dummy region is provided. Lower interconnection structures are formed in the cell region and the dummy region. One or more first multilayered structure patterns are formed in the cell region and one or more second multilayered structure patterns in the dummy region over the lower interconnection structures. The first multilayered structure patterns and second multilayered structure patterns extend in a first direction. Each of the second multilayered structure patterns includes an etch target layer. An insulating material layer is formed over the first multilayered structure patterns and the second multilayered structure patterns. An interlayer insulating layer that fills a space between two adjacent patterns of the first multilayered structure patterns and second multilayered structure patterns is formed by planarizing the insulating material layer. The etch target layer in each of the second multilayered structure patterns is removed.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: May 7, 2019
    Assignee: SK HYNIX INC.
    Inventors: Young Seok Ko, Soo Gil Kim, Joo Young Moon
  • Patent number: 10283713
    Abstract: A deposition mask assembly includes a frame including a first opening portion and a second opening portion spaced apart from each other in a first direction, a first split mask group including a plurality of first split masks arranged on the first opening portion in a second direction crossing the first direction, and a second split mask group including a plurality of second split masks arranged on the second opening portion in the second direction, wherein a boundary between adjacent first split masks in the second direction and a boundary between adjacent second split masks in the second direction are at different positions.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: May 7, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Su Hwan Lee, Eun Ho Kim
  • Patent number: 10256338
    Abstract: A semiconductor device includes a semiconductor substrate, a first epitaxial layer of a first conductivity type, a first semiconductor region of the first conductivity type, a second epitaxial layer of a second conductivity type, a second semiconductor region of the first conductivity type, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode; and a gate electrode pad. The first semiconductor region is not provided beneath the gate electrode pad.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 9, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeharu Koga
  • Patent number: 10249447
    Abstract: A process is provided for manufacturing an alkaline-based hybrid supercapacitor type battery, to an alkaline-based hybrid supercapacitor type battery, and to a process for recycling a negative electrode of an alkali-ion battery. The process for manufacturing the alkaline-based hybrid supercapacitor type battery comprises forming a negative electrode A from an electrode material B originating from a used alkali-ion battery having lost at least some of its initial capacity. Embodiments of the present disclosure are in particular applicable to the field of batteries.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: April 2, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Matthieu Picot, Philippe Azais
  • Patent number: 10242894
    Abstract: Apparatus, systems, and processes for substrate breakage detection in a thermal processing system are provided. In one example implementation, a process can include: accessing data indicative of a plurality of temperature measurements for a substrate, the plurality of measurements obtained during a cool down period of a thermal process; estimating one or more metrics associated with a cooling model based at least in part on the data indicative of the plurality of temperature measurements; and determining a breakage detection signal based at least in part on the one or more metrics associated with the cooling model. The breakage detection signal is indicative of whether the substrate has broken during thermal processing.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: March 26, 2019
    Assignee: Mattson Technology, Inc.
    Inventor: Joseph Cibere
  • Patent number: 10242875
    Abstract: A diffusion agent composition that, even when a semiconductor substrate which is an object into which an impurity diffusion ingredient is to be diffused has, on a surface thereof, a three-dimensional structure having nano-scale fine voids on a surface thereof, can be evenly coated on the whole area of an inner surface of the fine voids, whereby boron can be diffused into the semiconductor substrate, and a method for manufacturing a semiconductor substrate using the composition. The composition includes an impurity diffusion ingredient and a hydrolyzable Si compound to produce a silanol group, the impurity diffusion ingredient containing a complex compound containing boron having a specific structure.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: March 26, 2019
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Yoshihiro Sawada, Yu Takahashi, Takuya Ohhashi
  • Patent number: 10243176
    Abstract: A method for repairing a bank during manufacture of an organic EL display device when a bank defect portion is produced due to collapsing of a bank, a foreign particle, or the like. The method includes: detecting a defect portion of a lengthwise bank formed over a ground substrate; and when a defect portion is detected, forming, in each of adjacent concave spaces between which the lengthwise bank having the defect portion is located, a dam partitioning the concave space into a first space in a vicinity of the bank defect portion and a second portion not in the vicinity of the bank defect portion. The shape of the dam is configured so that in ejecting organic functional layer ink in each concave space with a nozzle head, there is an ink dropping point in each of the first space and the second space.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: March 26, 2019
    Assignee: JOLED INC.
    Inventors: Yoshiki Hayashida, Kazuhiro Kobayashi, Toshiaki Onimaru, Takayuki Shimamura