Patents Examined by David E. Graybill
  • Patent number: 11271129
    Abstract: Methods of fabricating emitter regions of solar cells using surface treatments, and the resulting solar cells, are described herein. In an example, a method of fabricating a solar cell includes treating a surface of a silicon substrate to form a lyophilic area between two lyophobic areas and depositing a liquid phase material containing a silicon material in the lyophilic area to form an emitter region.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: March 8, 2022
    Assignee: Total Marketing Services
    Inventor: Nils-Peter Harder
  • Patent number: 11244893
    Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: February 8, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fran├žois Tailliet, Guilhem Bouton
  • Patent number: 11211304
    Abstract: In an embodiment, an assembly includes an electronic component, a fixing member, a resilient member and a substrate having a first surface. The electronic component includes a heat-generating semiconductor device, a die pad and a plastic housing. The heat-generating semiconductor device is mounted on a first surface of the die pad, and the die pad is at least partially embedded in the plastic housing. The resilient member is engaged under compression between an upper side of the electronic component and a lower surface of the fixing member and the fixing member secures the electronic component to the first surface of the substrate.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: December 28, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Guenther Lohmann, Bernd Schmoelzer, Fabian Schnoy
  • Patent number: 11201145
    Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, an active well, an emitter, a base, a collector, a body contact region, and a blocking well. The semiconductor substrate may have a first conductive type. The active well may be formed in the semiconductor substrate. The active well may have a second conductive type. The emitter and the base may be formed in the active well. The collector may be formed in the semiconductor substrate outside the active well. The body contact region may be formed in the semiconductor substrate to electrically connect the collector with the semiconductor substrate. The body contact region may have a conductive type substantially the same as that of the collector. The blocking well may be configured to surround an outer wall of the body contact region. The blocking well may have the second conductive type.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 14, 2021
    Assignee: SK hynix Inc.
    Inventors: Joung Cheul Choi, Jae Young You
  • Patent number: 11195766
    Abstract: A method for manufacturing a combined semiconductor device. The method includes providing a semiconductor substrate, providing a protective layer or a protective layer stack in a non-CMOS area of the semiconductor substrate, wherein the non-CMOS area is portion of the semiconductor substrate reserved for a non-CMOS device, at least partially manufacturing a CMOS device in a CMOS area of the semiconductor substrate, the non-CMOS area and the CMOS area being different from each other, removing the protective layer or the protective layer stack, to expose the semiconductor substrate in the non-CMOS area, and manufacturing a non-CMOS device in the non-CMOS area of the semiconductor substrate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 7, 2021
    Assignee: Infineon Technologies AG
    Inventors: Dmitri Alex Tschumakow, Claus Dahl
  • Patent number: 11189573
    Abstract: A semiconductor package is described herein with electromagnetic shielding using metal layers and vias. In one example, the package includes a silicon substrate having a front side and a back side, the front side including active circuitry and an array of contacts to attach to a substrate, a metallization layer over the back side of the die to shield active circuitry from interference through the back side, and a plurality of through-silicon vias coupled to the back side metallization at one end and to front side lands of the array of lands at the other end to shield active circuitry from interference through the sides of the die.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Vijay K. Nair, Digvijay Raorane
  • Patent number: 11177373
    Abstract: A semiconductor device is manufactured with high mass productivity at low cost. Yield in a manufacturing process of the semiconductor device is improved. An island-shaped metal oxide layer is formed over a substrate, a resin layer is formed over the metal oxide layer to cover an end portion of the metal oxide layer, and the metal oxide layer and the resin layer are separated by light irradiation. After forming the resin layer and before the light irradiation, an insulating layer is formed over the resin layer. For example, the resin layer is formed in an island shape and the insulating layer is formed to cover an end portion of the resin layer. In the case where an adhesive layer is formed over the resin layer, the adhesive layer is preferably formed to be located inward from the end portion of the metal oxide layer.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: November 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiro Katayama, Masayoshi Dobashi, Masataka Nakada
  • Patent number: 11177437
    Abstract: An intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate structure includes an alignment assisting marker arranged in the second area. The intermediate structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate structure includes a resist arranged on the hard mask layer in the first area.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hao Tang, Michael Rizzolo, Injo Ok, Theodorus E. Standaert
  • Patent number: 11165017
    Abstract: A replacement bottom electrode structure process is provided in which a patterned stack containing a MTJ pillar and a top electrode structure is fabricated and passivated on a sacrificial dielectric material plug that is embedded in a dielectric capping layer. The sacrificial dielectric material plug is then removed and replaced with a bottom electrode structure. The replacement bottom electrode structure process of the present application allows the MTJ patterning to be misalignment tolerate and fully eliminates the potential yield loss from the bottom electrode structure.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Takashi Ando, Dimitri Houssameddine, Alexander Reznicek, Jingyun Zhang, Choonghyun Lee
  • Patent number: 11164881
    Abstract: In a non-limiting embodiment, a memory array is provided having a transistor device. The transistor device includes transistor device first, second and third doped regions in a substrate. The transistor device further includes a first transistor device select gate over a region between the transistor device first doped region and the transistor device second doped region, and a second transistor device select gate over a region between the transistor device first doped region and the transistor device third doped region. The transistor device further includes a transistor device dielectric barrier extending between the first transistor device select gate and the second transistor device select gate. A width of the dielectric barrier compared to a width of the first transistor device select gate and/or the second transistor device select gate may have a ratio ranging from 0.33:1 to 5:1.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: November 2, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Danny Pak-Chum Shum
  • Patent number: 11158800
    Abstract: A method for patterning a quantum dot layer, a method for manufacturing a display device and a transfer template are provided in embodiments of the disclosure; the method for patterning a quantum dot layer, comprising: preparing a quantum dot layer on a substrate, the quantum dot layer comprising a reserved portion and a portion to be removed; bonding the portion to be removed with a plurality of convex portions provided on a transfer template, by pressing the transfer template against the quantum dot layer; and removing the portion to be removed with a removal of the transfer template, while retaining the reserved portion on the substrate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 26, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhuo Chen, Yuanming Zhang, Wenhai Mei
  • Patent number: 11120997
    Abstract: Generally, this disclosure provides examples relating to tuning etch rates of dielectric material. In an embodiment, a dielectric material is conformally deposited in first and second trenches in a substrate. Merged lateral growth fronts of the first dielectric material in the first trench form a seam in the first trench. The dielectric material is treated. The treating causes a species to be on first and second upper surfaces of the dielectric material in the first and second trenches, respectively, to be in the seam, and to diffuse into the respective dielectric material in the first and second trenches. After the treating, the respective dielectric material is etched. A ratio of an etch rate of the dielectric material in the second trench to an etch rate of the dielectric material in the first trench is altered by presence of the species in the dielectric material during the etching.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chiang Chen, Chun-Hung Lee, Ryan Chia-jen Chen, Hung-Wei Lin, Lung-Kai Mao
  • Patent number: 11121241
    Abstract: A semiconductor device includes a semiconductor substrate having first and second main surfaces, a first region formed in a surface layer of the first main surface, a drift layer disposed adjacent to the first region, a charge accumulation region having a higher concentration than the drift region, and a trench gate including a trench penetrating the first region and the charge accumulation region, and a gate electrode formed in the trench. The trench gate includes a main trench having a gate electrode to which a gate voltage is applied, and a dummy trench having a gate electrode to which a voltage different from the main trench is applied. The main trench and the dummy trench sandwiches the charge accumulation region, and a contact area S1 between the dummy trench and the charge accumulation region is larger than a contact area S2 between the main trench and the charge accumulation region.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: September 14, 2021
    Assignee: DENSO CORPORATION
    Inventor: Hiromitsu Tanabe
  • Patent number: 11114566
    Abstract: A semiconductor device includes a substrate, a first fin, a second fin, a dummy fin, a first metal gate, a second metal gate, and an isolation structure. The first, the second and the dummy fins are on the substrate, and the dummy fin is disposed between the first fin and the second fin. The first metal gate and the second metal gate are over the first fin and the second fin, respectively. The isolation structure is on the dummy fin, and the dummy fin and the isolation structure separate the first metal gate and the second metal gate.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Kai-Chieh Yang, Chia-Wei Su, Jia-Ni Yu, Wei-Hao Wu, Chih-Hao Wang
  • Patent number: 11101354
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region and extends over the isolation structure, the semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, the first doped region extends across the first active region, the spacing region is over the isolation structure, and the spacing region is an undoped region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Cheng-Yeh Huang, Chin-Nan Chang, Chih-Ming Lee, Chi-Yen Lin
  • Patent number: 11075154
    Abstract: A semiconductor device includes: a lead frame that has one end in contact with the upper surface of the second terminal of the semiconductor element in the sealing portion, and that has the other end exposed from the sealing portion; and a control conductive bonding material that bonds between the upper surface of the second terminal of the semiconductor element and the one end of the lead frame, and the control conductive bonding material having electric conductivity.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: July 27, 2021
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Soichiro Umeda, Atsushi Kyutoku
  • Patent number: 11062960
    Abstract: Devices and methods are provided for fabricating shared contact trenches for source/drain layers of n-type and p-type field-effect transistor devices, wherein the shared contact trenches include dual silicide layers and dual epitaxial layers. For example, a semiconductor device includes first and second field-effect transistor devices having respective first and second source/drain layers, and a shared contact trench, wherein the first and second source/drain layers are disposed adjacent to each other within the shared contact trench, and are commonly connected to each other by the shared contact trench. The shared contact trench includes a first silicide contact layer disposed on the first source/drain layer, and a second silicide contact layer disposed on the second source/drain layer, wherein the first and second silicide contact layers comprise different silicide materials, and a metallic fill layer disposed on the first and second silicide contact layers.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Kangguo Cheng, Junli Wang, Zuoguang Liu
  • Patent number: 11037911
    Abstract: A light emitting device includes a wiring substrate, light emitting elements, light-reflecting films, and a light diffusing member. The light emitting elements are mounted in a matrix on the wiring substrate. Each of the light emitting elements includes a sapphire substrate having a lower surface, first lateral surfaces inclined to the lower surface, and second lateral surfaces perpendicular to the lower surface, and a semiconductor layered structure disposed on the lower surface. The light-reflecting films are respectively disposed on the light emitting elements. The light diffusing member is disposed above the light emitting elements. At least a group of the light emitting elements is arranged such that, in every adjacent ones of the light emitting elements in at least one of a row direction and a column direction, the first lateral surface of the light emitting element faces the second lateral surface of the adjacent light emitting element.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 15, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Motokazu Yamada
  • Patent number: 11028473
    Abstract: A method of manufacturing a semiconductor device includes forming a seed layer containing a predetermined element on a substrate by performing a process a predetermined number of times, and supplying a second precursor containing the predetermined element and not containing the ligand to the substrate to form a film containing the predetermined element on the seed layer. The process includes alternately performing: supplying a first precursor to the substrate to form an adsorption layer of the first precursor, the first precursor containing the predetermined element and a ligand which is coordinated to the predetermined element and which contains at least one of carbon or nitrogen, and supplying a ligand desorption material to the substrate to desorb the ligand from the adsorption layer of the first precursor.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: June 8, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Ryuji Yamamoto, Yoshiro Hirose
  • Patent number: 11024785
    Abstract: Solid state light emitting devices including light-emitting diodes (LEDs), and more particularly packaged LEDs are disclosed. In some embodiments, an LED package includes electrical connections that are configured to reduce corrosion of metals within the LED package; or decrease the overall forward voltage of the LED package; or provide an electrical path for serially-connected electrostatic discharge (ESD) chips. In some embodiments, an LED package includes at least two LED chips and a material between the two LED chips that promotes homogeneity of composite emissions from the two LED chips. In this manner, LED packages according to the present disclosure may be beneficial for various applications, including those where a high luminous intensity is desired in a variety of environmental conditions. Such applications include automotive lighting, aerospace lighting, and general illumination.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: June 1, 2021
    Assignee: CreeLED, Inc.
    Inventors: Roshan Murthy, Kenneth M. Davis, Jae-Hyung Park, Xiameng Shi