Abstract: A substrate processing method which can clean a peripheral portion of a substrate after polishing and can check the cleaning effect of the peripheral portion of the substrate is disclosed. The substrate processing method includes polishing a peripheral portion of the substrate by pressing a polishing tape having abrasive grains against the peripheral portion of the substrate with a first head, cleaning the peripheral portion of the substrate by supplying a cleaning liquid to the peripheral portion of the substrate after polishing, bringing a tape having no abrasive grains into contact with the peripheral portion of the substrate after cleaning by a second head, applying light to the tape and receiving reflected light from the tape by a sensor, and judging that the peripheral portion of the substrate is contaminated when an intensity of the received reflected light is lower than a predetermined value.

Abstract: To improve reliability of a semiconductor device, in a method of manufacturing the semiconductor device, a ground plane region of an n-type MISFET is formed by ion-implanting a p-type impurity and nitrogen (N) and a ground plane region of a p-type MISFET is formed by ion-implanting an n-type impurity and one of carbon (C) and fluorine (F).

Abstract: The display panel includes a light emitting device, three quantum dot converters including quantum dot particles and converting light of a first color emitted from the light emitting device to light of a different color and emitting the light of the different color, a transmission part transmitting light of the first color emitted from the light emitting device, and a transparent substrate disposed on one side of the three quantum dot converters and the transmission part. One of the three quantum dot converters emits a white light to the transparent substrate.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

Abstract: A vertical type light emitting element is disclosed. The vertical type light emitting element includes: a color conversion electrode part including a first electrode pad and a color conversion layer; a reflective electrode part including a second electrode pad and a reflective layer; and a light emitting semiconductor part interposed between the color conversion electrode part and the reflective electrode part. The color conversion electrode part further includes an electrically conductive light transmissive plate. The first electrode pad and the color conversion layer are interposed between the light transmissive plate and the upper surface of the light emitting semiconductor part. Roughnesses are formed on the upper surface of the light emitting semiconductor part bordering the color conversion electrode part to increase the amount of light entering the color conversion electrode part through the light emitting semiconductor part.

Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.

Abstract: Embodiments of this disclosure are directed to a multi-gate gallium nitride (GaN) transistor and methods of making the same. The multi-gate GaN transistor includes a gallium nitride layer. The GaN transistor includes two or more gate electrodes between a drain electrode and a source electrode. A polarization layer is located between the first gate electrode and the second gate electrode, the polarization layer forming a two dimensional electron gas (2DEG) within the GaN layer, the 2DEG electrically coupling the first gate electrode and the second gate electrode.

Abstract: A dressing device including: a disk that has an opening on an inside, the disk dressing a polishing surface for polishing a substrate; a rotatable holder, the disk being coupled to a lower surface side of the holder, the holder being provided with a first flow passage that passes from a lower surface to an upper surface, the lower surface being inside an outer edge of the opening of the disk; and a housing that is provided with a distance from the upper surface of the holder, the housing being provided with a second flow passage in an interior, the housing being fixed such that an opening of the second flow passage faces the upper surface of the holder, the second flow passage being connected with a supply source and a suction source of process liquid.

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

Abstract: The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over a top of the fin and laterally adjacent sidewalls of the fin. An N-type gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin, the N-type gate electrode comprising a P-type metal layer on the gate dielectric layer, and an N-type metal layer on the P-type metal layer. A first N-type source or drain region is adjacent a first side of the gate electrode. A second N-type source or drain region is adjacent a second side of the gate electrode, the second side opposite the first side.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.

Abstract: By sequentially performing, a plurality of times, a step of supplying a mixed gas of an organic metal-containing source gas and an inert gas to a process chamber housing a substrate by adjusting a flow velocity of the mixed gas on the substrate to 7.8 m/s to 15.6 m/s and adjusting a partial pressure of the organic metal-containing source gas in the mixed gas to 0.167 to 0.3, a step of exhausting the process chamber, a step of supplying an oxygen-containing gas to the process chamber, and a step of exhausting the process chamber, a metal oxide film is formed on the substrate.

Abstract: In a back-illuminated solid-state image pickup device, a first group of charge transfer electrodes (vertical shift register) is present in an imaging region, and a second group of charge transfer electrodes (horizontal shift register) is present in a peripheral region around the imaging region. The light incident surface of the semiconductor substrate 4 corresponding to the peripheral region is etched, and an inorganic light shielding substance SH is filled in the etched region. The amount of the inorganic light shielding substance that evaporates and vaporizes under the vacuum environment is extremely small, and the influence on the imaging by the vaporized gas is small.

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

Abstract: Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including elevated temperatures associated with a read or write operation of a neighboring cell, corrupting the data stored in them. To prevent this thermal disturb effect, memory cells may be separated from one another by thermally insulating regions that include one or several interfaces. The interfaces may be formed by layering different materials upon one another or adjusting the deposition parameters of a material during formation. The layers may be created with planar thin-film deposition techniques, for example.

Abstract: An intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate structure includes an alignment assisting marker arranged in the second area. The intermediate structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate structure includes a resist arranged on the hard mask layer in the first area.

Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing a substrate to a blocking molecule to selectively deposit a blocking layer on the first surface. A layer is selectively formed on the second surface and defects of the layer are formed on the blocking layer. The defects are removed from the blocking layer on the first surface.