Patents Examined by David E. Graybill
  • Patent number: 10622326
    Abstract: A chip package structure includes a chip package layer and at least one conductive structure layer. The chip package layer includes at least one chip and an encapsulant. The chip has an upper surface, and the encapsulant is used to encapsulate the chip and expose the upper surface. The conductive structure layer includes a plurality of first conductive pillars and a plurality of second conductive pillars. The first conductive pillars are disposed on the upper surface, the second conductive pillars are disposed on the upper surface and located between an edge of the upper surface and the first conductive pillars. A density of the second conductive pillars along an extending direction of the edge is greater than or equal to 1.2 times of a density of the first conductive pillars along the extending direction of the edge.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: April 14, 2020
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Chen-Tsai Yang, Ko-Chin Yang, Jui-Chang Chuang, Yen-Ting Wu, Chia-Hua Lu
  • Patent number: 10613135
    Abstract: A semiconductor device including: an insulating substrate; a semiconductor element mounted on the insulating substrate; an internal printed circuit board disposed on the semiconductor element; and a sealing member that seals the semiconductor element, the internal printed circuit board, and at least a portion of the insulating substrate. The sealing member is made of a sealant that includes a resin and a pigment, and that initially has a chromatic, white, or gray color, and the sealing member degrades, thereby causing color of a front surface thereof to change to a degree recognizable by a user after the semiconductor device has been in use under a prescribed condition for a prescribed duration.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: April 7, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuji Takematsu, Kenji Okamoto
  • Patent number: 10615265
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Tahir Ghani, Byron Ho, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10607833
    Abstract: There is provided a method of manufacturing a semiconductor device, including forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing supplying a precursor gas to the substrate; and supplying a first oxygen-containing gas to the substrate. Further, the act of supplying the precursor gas includes a time period in which the precursor gas and a second oxygen-containing gas are simultaneously supplied to the substrate.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: March 31, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Katsuyoshi Harada, Takashi Ozaki, Masato Terasaki, Risa Yamakoshi, Satoshi Shimamoto, Jiro Yugami, Yoshiro Hirose
  • Patent number: 10607861
    Abstract: A method for wafer dicing and removing separated integrated circuit (IC) dies from a carrier substrate includes mounting a wafer on a substrate using an adhesive layer, laser scribing the adhesive layer to create defect regions in the adhesive layer, and performing a breaking step to separate the laser-scribed adhesive layer into separated adhesive portions corresponding to the IC dies. For a stealth-dicing (SD) technique, defect regions also are created in the wafer using a laser and the breaking step is an expansion step that simultaneously separates the dies and corresponding portions of adhesive. For a dice-before-grind (DBG) technique, the dies are separated by backside grinding before the breaking step. Efficient adhesive-layer separation is achieved with reduced backside chipping associated with conventional blade dicing.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: March 31, 2020
    Assignee: NXP B.V.
    Inventors: Siriluck Wongratanaporngoorn, Yao Jung Chang, Ekapong Tangpattanasaeree, Paradee Jitrungruang, Pitak Seantumpol
  • Patent number: 10600876
    Abstract: A method includes forming a first cavity having a first width and a second cavity having a second width greater than the first width in a dielectric material, forming a first conformal layer in the first and second cavities, forming spacers in the first and second cavities, the spacers covering a first portion of the first conformal layer positioned on sidewalls of the first and second cavities and exposing a second portion of the first conformal layer positioned on the sidewalls of the first and second cavities, forming a material layer in the first and second cavities to cover bottom portions of the first conformal layer, performing a first etch process to remove the second portion of the first conformal layer positioned on the sidewalls of the first and second cavities, removing the spacers and the material layer, and forming a fill material in the first and second cavities.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: March 24, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Guowei Xu, Hui Zang, Rongtao Lu
  • Patent number: 10593781
    Abstract: The present disclosure provides a method for forming a semiconductor device, including: providing a substrate; forming a gate material layer over the substrate; performing a first etching process on the gate material layer to remove a first portion of the gate material layer and expose a first portion of the substrate; performing a first ion implantation process on the first portion of the substrate to form a body region in the substrate, the body region being doped with first dopant ions and extending to under a remaining portion of the gate material layer; and forming a gate electrode by performing a second etching process on the remaining portion of the gate material layer to remove a second portion of the gate material layer, the second portion of the gate material layer being located on a side away from the body region.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: March 17, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: De Yan Chen, Yan Chun Ma, Dae-Sub Jung
  • Patent number: 10580967
    Abstract: A magnetic tunnel junction device includes a pinned magnetic layer, a free magnetic layer embodied as a synthetic antiferromagnetic device, and a nonmagnetic barrier layer sandwiched between the pinned magnetic layer and the free magnetic layer. The free magnetic layer includes a first ferromagnetic layer, a second ferromagnetic layer and a nonmagnetic spacing layer sandwiched between them; and can transform from the antiferromagnetic state to the ferromagnetic state regulated by electric field. Under the coaction of the electric field and the current, the ferromagnetic layer close to the barrier layer of the magnetic tunnel junction is switched to write in data. Also, a magnetic random access memory based on a synthetic antiferromagnetic free layer can write in data under the coaction of the electric field and the current, and has advantages such as simple structure, low power consumption, rapid speed, radiation resistant, and non-volatility.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: March 3, 2020
    Assignee: XI'AN JIAOTONG UNIVERSITY
    Inventors: Tai Min, Xue Zhou, Lin Zhang, Lei Wang
  • Patent number: 10566209
    Abstract: An etching method can protect a mask with a material having higher etching resistance to a silicon-containing film. The etching method is performed in a state that a processing target object is placed within a chamber main body. The etching method includes forming a tungsten film on the processing target object and etching the silicon-containing film of the processing target object. The forming of the tungsten film includes supplying a gaseous tungsten-containing precursor onto the processing target object; and generating plasma of a hydrogen gas to supply active species of hydrogen to the precursor on the processing target object. In the etching of the silicon-containing film, plasma of a processing gas containing fluorine, hydrogen and carbon is generated within the chamber main body.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: February 18, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yu Nagatomo, Yoshihide Kihara
  • Patent number: 10566246
    Abstract: Devices and methods are provided for fabricating shared contact trenches for source/drain layers of n-type and p-type field-effect transistor devices, wherein the shared contact trenches include dual silicide layers and dual epitaxial layers. For example, a semiconductor device includes first and second field-effect transistor devices having respective first and second source/drain layers, and a shared contact trench, wherein the first and second source/drain layers are disposed adjacent to each other within the shared contact trench, and are commonly connected to each other by the shared contact trench. The shared contact trench includes a first silicide contact layer disposed on the first source/drain layer, and a second silicide contact layer disposed on the second source/drain layer, wherein the first and second silicide contact layers comprise different silicide materials, and a metallic fill layer disposed on the first and second silicide contact layers.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Kangguo Cheng, Junli Wang, Zuoguang Liu
  • Patent number: 10566242
    Abstract: A plasma doping process provides conformal doping profiles for lightly doped source/drain regions in fins, and reduces the plasma doping induced fin height loss. The plasma doping process overcomes the limitations caused by traditional plasma doping processes in fin structures that feature aggressive aspect ratios and tights pitches. Semiconductor devices with conformal lightly doped S/D regions and reduced fin height loss demonstrate reduced parallel resistance (Rp) and improved transistor performance.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: February 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ling Chan, Tsan-Chun Wang, Liang-Yin Chen, Huicheng Chang
  • Patent number: 10553571
    Abstract: Backplane-side bonding structures including a common metal are formed on a backplane. Multiple source coupons are provided such that each source coupon includes a transfer substrate and an array of devices to be transferred. Each array of devices are arranged such that each array includes a unit cell structure including multiple devices of the same type and different types of bonding structures including different metals that provide different eutectic temperatures with the common metal. Different types of devices can be sequentially transferred to the backplane by sequentially applying the supply coupons and selecting devices providing progressively higher eutectic temperatures between respective bonding pads and the backplane-side bonding structures. Previously transferred devices stay on the backplane during subsequent transfer processes, enabling formation of arrays of different devices on the backplane.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: February 4, 2020
    Assignee: GLO AB
    Inventors: Anusha Pokhriyal, Sharon N. Farrens
  • Patent number: 10553562
    Abstract: Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: February 4, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Mariam Sadaka
  • Patent number: 10553749
    Abstract: A nitride-based semiconductor light-emitting device comprises a light-emitting stack comprising a first semiconductor structure having a first conductivity, a second semiconductor structure having a second conductivity, and an active region between the first semiconductor structure and the second semiconductor structure; a semiconductor buffer structure formed under the first semiconductor structure; an un-doped AlGaN layer formed between the first semiconductor structure and the semiconductor buffer structure; and a substrate under the semiconductor buffer structure, wherein the semiconductor buffer structure comprises an un-doped first layer under the un-doped AlGaN layer, and an un-doped second layer between the un-doped first layer and the substrate, and wherein the thickness of the un-doped first layer is thicker than that of the un-doped second layer and the un-doped AlGaN layer.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: February 4, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Wen Hsiang Lin, Chang-Hua Hsieh
  • Patent number: 10553411
    Abstract: An ion collector includes a plurality of segments and a plurality of integrators. The plurality of segments are physically separated from one another and spaced around a substrate support. Each of the segments includes a conductive element that is designed to conduct a current based on ions received from a plasma. Each of the plurality of integrators is coupled to a corresponding conductive element. Each of the plurality of integrators is designed to determine an ion distribution for a corresponding conductive element based, at least in part, on the current conducted at the corresponding conductive element. An example benefit of this embodiment includes the ability to determine how uniform the ion distribution is across a wafer being processed by the plasma.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: February 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Otto Chen, Chi-Ying Wu, Chiah-Chih Chen
  • Patent number: 10522348
    Abstract: Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: December 31, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, Raghupathy Giridhar
  • Patent number: 10510540
    Abstract: Methods of forming semiconductor devices comprising etching a hardmask and spin-on-carbon layer through an opening in a photoresist to expose a gapfill material. The photoresist, spin-on-carbon layer and gapfill material are removed. A new spin-on-carbon layer, hardmask and photoresist are formed with an opening over a spacer mandrel. The hardmask, spin-on-carbon layer are etched through the opening and the layers and spacer mandrel are removed. An etch stop layer and oxide layer are removed and a height of the spacer mandrel and gapfill material are reduced exposing portions of the substrate. The exposed portions of the substrate are fin etched and the layers removed.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: December 17, 2019
    Assignee: MICROMATERIALS LLC
    Inventors: Ying Zhang, Qingjun Zhou, Yung-Chen Lin, Ho-yung David Hwang
  • Patent number: 10446401
    Abstract: Reliability of a semiconductor device is improved. In a method of manufacturing a semiconductor device, nitrogen is introduced into a surface of a substrate and a sacrificial film is formed on the surface in a field effect transistor formation region different from a memory transistor formation region. Subsequently, the sacrificial film is removed to remove the nitrogen introduced in the surface of the substrate in the field effect transistor formation region.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 15, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideki Makiyama
  • Patent number: 10431686
    Abstract: An integrated circuit (IC) employs a channel structure layout having an active semiconductor channel structure(s) and an isolated neighboring dummy semiconductor channel structure(s) for increased uniformity. A semiconductor channel structure(s) in an IC is a fin structure(s) or a gate-all-around (GAA) structure(s) employed in a Field-Effect Transistor (FET), such as a FinFET or a three-dimensional (3D) FET. The channel structures in the IC are fabricated according to a circuit cell architecture, such as a standard circuit cell (“standard cell”). The IC includes an active (e.g., diffusion) region in which a semiconductor channel structure array (e.g., semiconductor fin array) is formed according to a pattern. The IC includes a device employing a channel structure array in the active region. The channel structure array may include one active channel structure (e.g., fin) for reduced power consumption in the FinFET, and may include at least one dummy fin for increased uniformity.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Haining Yang, Xiangdong Chen
  • Patent number: 10424505
    Abstract: Provided herein is a method of manufacturing a semiconductor device. The method may include forming an amorphous channel layer. The method may include forming a diffusion barrier on the amorphous channel layer. The method may include forming an amorphous seed layer on the diffusion barrier. The method may include forming a seed layer by crystallizing the amorphous seed layer. The method may include forming a channel layer by crystallizing the amorphous channel layer.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: September 24, 2019
    Assignee: SK hynix Inc.
    Inventors: Yong Woo Lee, Jin Ha Kim