Abstract: Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including elevated temperatures associated with a read or write operation of a neighboring cell, corrupting the data stored in them. To prevent this thermal disturb effect, memory cells may be separated from one another by thermally insulating regions that include one or several interfaces. The interfaces may be formed by layering different materials upon one another or adjusting the deposition parameters of a material during formation. The layers may be created with planar thin-film deposition techniques, for example.

Abstract: Apparatus, systems, and processes for substrate breakage detection in a thermal processing system are provided. In one example implementation, a process can include: accessing data indicative of a plurality of temperature measurements for a substrate, the plurality of measurements obtained during a cool down period of a thermal process; estimating one or more metrics associated with a cooling model based at least in part on the data indicative of the plurality of temperature measurements; and determining a breakage detection signal based at least in part on the one or more metrics associated with the cooling model. The breakage detection signal is indicative of whether the substrate has broken during thermal processing.

Abstract: The present invention provides a light emitting device which emit light having a high-order level without increasing a current injection density to an active layer. A light emitting device according to the present invention includes an upper electrode layer, a lower electrode layer, and an active layer provided between them. In this case, light is emitted by injection of electric current to the active layer through the upper electrode layer and the lower electrode layer, the active layer has a plurality of quantum-confined structures, and a first quantum-confined structure has a ground level having an energy level E0 and a high-order level having an energy level E1, and a second quantum-confined structure has an energy level E2 which is higher than the E0, and the E1 and the E2 are substantially matched.

Abstract: A method of fabricating a semiconductor device. A wafer having a front side and a back side opposite to the front side is prepared. A plurality of through substrate vias (TSVs) is formed on the front side. A redistribution layer (RDL) is then formed on the TSVs. The wafer is bonded to a carrier. A wafer back side grinding process is performed to thin the wafer on the back side. An anneal process is performed to recrystallize the TSVs. A chemical-mechanical polishing (CMP) process is performed to polish the back side.

Abstract: Backplane-side bonding structures including a common metal are formed on a backplane. Multiple source coupons are provided such that each source coupon includes a transfer substrate and an array of devices to be transferred. Each array of devices are arranged such that each array includes a unit cell structure including multiple devices of the same type and different types of bonding structures including different metals that provide different eutectic temperatures with the common metal. Different types of devices can be sequentially transferred to the backplane by sequentially applying the supply coupons and selecting devices providing progressively higher eutectic temperatures between respective bonding pads and the backplane-side bonding structures. Previously transferred devices stay on the backplane during subsequent transfer processes, enabling formation of arrays of different devices on the backplane.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a sealing member configured to cover a lower surface of the semiconductor layer and a side surface of the semiconductor layer to protrude to be higher than an upper surface of the semiconductor layer at a side of the semiconductor layer, a fluorescer layer provided above the semiconductor layer and the sealing member, and an insulating film provided between the sealing member and the semiconductor layer and between the sealing member and the fluorescer layer. A corner of a protruding portion of the sealing member is rounded.

Abstract: A first and second vertical fin are formed on a substrate structure. A dielectric layer is disposed on the substrate structure and the first and second vertical fins. A work function metal (WFM) layer is disposed on the dielectric layer. A first sidewall spacer and a second sidewall space are formed proximate to the first vertical fin and the second vertical fin, respectively. A lithographic mask is applied to a first area proximate to the first vertical fin including the first vertical fin, and a portion of the WFM layer proximate to the first vertical fin. A portion of the WFM layer proximate to the second sidewall spacer is recessed below an upper surface of the second sidewall spacer. The lithographic mask is removed. A portion of the dielectric layer is removed to produce a wimpy vertical transport device and a nominal vertical transport device on the substrate structure.

Abstract: An array substrate and a manufacturing method thereof, comprising a base substrate, and a gate, a gate insulating layer, an active layer and a source/drain arranged on the base substrate, the array substrate further comprising an antenna for receiving and/or transmitting wireless signals, the antenna being arranged on the base substrate. By arranging the antenna on the base substrate of the array substrate, the antenna is integrated directly in the display panel. Thus, not only the area of the PCB circuit board in the display device can be reduced, but also the spare area in the array substrate can be utilized sufficiently, thereby improving the integration level of the display device and reducing the total volume of the display device.

Abstract: A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further includes a source, a drain, and a gate between the source and the drain, the gate being over the III-N layer structure. The p-type III-N layer includes a first portion that is at least partially in a device access region between the gate and the drain, and the first portion of the p-type III-N layer is electrically connected to the source and electrically isolated from the drain. When the transistor is biased in the off state, the p-type layer can cause channel charge in the device access region to deplete as the drain voltage increases, thereby leading to higher breakdown voltages.

Abstract: Split-gate flash memory and forming method thereof are provided. The method includes: forming a first dielectric layer on a semiconductor substrate; forming a floating gate layer on the first dielectric layer; forming a mask layer on the floating gate layer; etching the mask layer until first groove exposing the floating gate layer is formed; forming a protective sidewall on sidewall of the first groove; forming a gate dielectric layer on bottom and the sidewall of the first groove; forming two control gates on the gate dielectric layer, the remained first groove serving as second groove; etching the gate dielectric layer and the floating gate layer at bottom of the second groove until third groove exposing the first dielectric layer is formed; forming a source in the semiconductor substrate under the third groove; and forming a second dielectric layer in the third groove. Reliability and durability of the memory are improved.

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided, and a dielectric layer is formed to cover the substrate. A recess portion is formed in the dielectric layer. A spacer is formed on a side surface of the recess portion. The dielectric layer is etched through the recess portion to form a hole in the dielectric layer to expose a portion of the substrate.

Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.

Abstract: A CZ silicon ingot is doped with donors and acceptors and includes an axial gradient of doping concentration of the donors and of the acceptors. An electrically active net doping concentration, which is based on a difference between the doping concentrations of the donors and acceptors varies by less than 60% for at least 40% of an axial length of the CZ silicon ingot due to partial compensation of at least 20% of the doping concentration of the donors by the acceptors.

Abstract: Methods of forming a layer of silicon germanium include forming an epitaxial layer of Si1-xGex on a silicon substrate, wherein the epitaxial layer of Si1-xGex has a thickness that is less than a critical thickness, hc, at which threading dislocations form in Si1-xGex on silicon; etching the epitaxial layer of Si1-xGex to form Si1-xGex pillars that define a trench in the epitaxial layer of Si1-xGex, wherein the trench has a height and a width, wherein the trench has an aspect ratio of height to width of at least 1.5; and epitaxially growing a suspended layer of Si1-xGex from upper portions of the Si1-xGex pillars, wherein the suspended layer defines an air gap in the trench beneath the suspended layer of Si1-xGex.

Abstract: A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.

Abstract: A semiconductor package having a second semiconductor package or module integrated therein. The semiconductor package of the present invention typically comprises active and passive devices which are each electrically connected to an underlying substrate. The substrate is configured to place such active and passive devices into electrical communication with contacts of the substrate disposed on a surface thereof opposite that to which the active and passive devices are mounted. The module of the semiconductor package resides within a complimentary opening disposed within the substrate thereof. The module and the active and passive devices of the semiconductor package are each fully or at least partially covered by a package body of the semiconductor package.

Abstract: A method for fabricating a semiconductor package, the method includes forming at least one conductive via having a first end and a second end opposite the first end in a wafer, in which the wafer has a first surface and a second surface opposite the first surface, and the first end of the at least one conductive via is exposed of the first surface of the wafer; grinding the second surface of the wafer to form an inner portion and a ring portion surrounding the inner portion of the wafer, wherein the inner portion has a thinner thickness than that of the ring portion; and etching the inner portion to expose the second end of the at least one conductive via.

Abstract: A method for manufacturing a metal insulator metal (MIM) trench capacitor, the method may include forming a cavity in an Intermetal Dielectric stack, wherein a bottom of the cavity exposes a lower metal layer; wherein the Intermetal Dielectric stack comprises a top dielectric layer; depositing a first metal layer on a bottom of a cavity and on sidewalls of the cavity; depositing a sacrificial layer over the first metal layer; filling the cavity with a filling material; removing, by a planarization process, a portion of the sacrificial layer positioned above the top dielectric layer and a portion of the first metal layer positioned above the top dielectric layer to expose an upper portion of the sacrificial layer and an upper portion of the first metal layer; forming a recess by removing the upper portion of the sacrificial layer and the upper portion the first metal layer while using the filling material as a mask; removing the filling material by a first removal process that is selective to the sacrificial l

Abstract: A method for fabricating an optical multi-chip module (MCM) includes temporarily curing an underfill material on a chip including an optical device to prevent flow of the underfill material. The chip is flip-chip mounted on a waveguide module having a mirror for directing light to or from the chip, wherein the underfill material is disposed between the chip and the waveguide module. The underfill material is cured to adhere the chip to the waveguide module.

Abstract: Solder-bumped semiconductor substrates (e.g., semiconductor wafers) and methods for forming solder bumped semiconductor substrates are provided, in which solder bumps are formed on a semiconductor substrate using preformed solder balls having different compositions and/or sizes. Two or more solder balls masks are successively utilized to place different types of preformed solder balls (differing in composition and/or size) into corresponding cavities of a solder ball fixture, and thereby form an array of different types of preformed solder balls arranged in the solder ball fixture. The array of preformed solder balls in the solder ball fixture are then transferred to corresponding contact pads of a semiconductor substrate (e.g., semiconductor wafer) using a single solder reflow process. This process allows different types of preformed solder bumps to be bonded to a semiconductor substrate at the same time using a single solder reflow process.