Patents Examined by David Lam
  • Three-dimensional memory device with logic signal routing through a memory die and methods of making the same
    Patent number: 10727215
    Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 28, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Kwang-Ho Kim, Johann Alsmeier
  • Bias scheme for dummy lines of data storage devices
    Patent number: 10726923
    Abstract: Systems and methods reduce latency during read-verify and programming operations by biasing a dummy line next to a neighboring bit line with an over-drive voltage during a first period and then biasing the dummy line to a same voltage as that of the neighboring bit line during a second period that contiguously follows the first period. The dummy line may be biased based on a state of the neighboring bit line. For example, a first dummy line is first charged to an over-drive voltage and then charged to the same voltage as that of a first neighboring bit line, and a second dummy line at an opposing edge is first charged to the over-drive voltage and then charged to the same voltage as that of a second neighboring bit line. This biasing scheme using the dummy lines helps reduce capacitive loading for neighboring bit lines during ready-verify and programming operations.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: July 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventor: Xiang Yang
  • Semiconductor structures, memory cells and devices comprising ferroelectric materials, systems including same, and related methods
    Patent number: 10726899
    Abstract: A semiconductor structure includes an electrode, a ferroelectric material adjacent the electrode, the ferroelectric material comprising an oxide of at least one of hafnium and zirconium, the ferroelectric material doped with bismuth, and another electrode adjacent the ferroelectric material on an opposite side thereof from the first electrode. Related semiconductor structures, memory cells, semiconductor devices, electronic systems, and related methods are disclosed.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Albert Liao, Wayne I. Kinney, Yi Fang Lee, Manzar Siddik
  • Semiconductor device configured to generate a strobe signal having various patterns
    Patent number: 10720192
    Abstract: A semiconductor device includes a strobe signal generation circuit. The strobe signal generation circuit generates a strobe signal which is toggled in synchronization with a multiplication clock signal during enablement periods of a toggling drive signal and a down drive signal. A postamble period is set according to the toggling drive signal and the down drive signal.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Young Jun Yoon
  • Non-volatile memory device and method for controlling the non-volatile memory device
    Patent number: 10720214
    Abstract: A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen Tseng, Tsung-Yu Yang, Chung-Jen Huang
  • System and method for programming non-volatile memory during burst sequential write
    Patent number: 10714169
    Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: July 14, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Phil Reusswig, Pitamber Shukla, Sarath Puthenthermadam, Mohan Dunga, Sahil Sharma, Rohit Sehgal, Niles Yang
  • Management of power state transitions of a memory sub-system
    Patent number: 10712806
    Abstract: A transitory idle state is established for a memory sub-system that can be transitioned from an active state to one or more idle states including the transitory idle state and a deep idle state. A power consumption metric and transition time for each idle state is identified. A transitional energy metric is determined for each idle state based on the corresponding power consumption metric transition time. An energy target time is determined for the transitory idle state. Based on the energy target time, an idle state optimization time is determined for the transitory idle state. The memory sub-system is maintained in the transitory idle state for a duration of the idle state optimization time.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kihoon Park, David A. Holmstrom
  • Dynamic 1-tier scan for high performance 3D NAND
    Patent number: 10714198
    Abstract: A method and system for executing a dynamic 1-tier scan on a memory array are provided. The memory array includes a plurality of memory cells organized into a plurality of sub-groups. The dynamic 1-tier scan includes executing an program loop in which cells of a first sub-group are counted to determine whether a numeric threshold is met, and, if the numeric threshold is met with respect to the first sub group, at least one additional program loop is executed in which cells of a second sub-group are counted to determine whether the numeric threshold is met with respect to the second sub-group.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: July 14, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Deepanshu Dutta, Huai-yuan Tseng
  • Memory device to execute read operation using read target voltage
    Patent number: 10699792
    Abstract: A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: June 30, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Maejima
  • Semiconductor device including volatile and non-volatile memory cells
    Patent number: 10685708
    Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang Hoon Jeon, Yoo Cheol Shin, Jun Hee Lim, Sung Kweon Baek, Chan Ho Lee, Won Chul Jang, Sun Gyung Hwang
  • Memory device with voltage controller
    Patent number: 10679702
    Abstract: A memory device includes a first memory area, a second memory area, a third memory area and a controller. The first memory area has a plurality of first memory cells sharing a first channel area. The second memory area has a plurality of second memory cells sharing the first channel area. The third memory area having a plurality of third memory cells sharing a second channel area, the second channel area being different from the first channel area, the first channel area and the second channel area being connected to a bit line. The controller is configured to input a voltage for the second memory cells to the second memory cells and a voltage for the third memory cells to the third memory cells, when a controlling operation is performed on the first memory cells, the voltages for the second and third memory cells having different magnitudes.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 9, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hun Kwak, Sang Wan Nam, Chi Weon Yoon
  • Lower power auto-zeroing receiver incorporating CTLE, VGA, and DFE
    Patent number: 10672437
    Abstract: An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: June 2, 2020
    Assignee: Integrated Device Technology, Inc.
    Inventor: Steven E. Finn
  • Dynamic reconfigurable dual power I/O receiver
    Patent number: 10672438
    Abstract: An apparatus is provided which comprises: a first circuitry to sample a first input signal to generate a first sampled signal, and to sample a second input signal to generate a second sampled signal, wherein the first input signal comprises data; a second circuitry to receive the first sampled signal and the second sampled signal, and to generate a first pair of differential signals; an offset cancellation circuitry to cancel or reduce an offset in the first pair of differential signals; and a latch to receive the first pair of differential signals subsequent to the cancellation or reduction of the offset, and to output a second pair of differential signals, wherein the second pair of differential signals is indicative of the data.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Mohammed G. Mostofa, Roger K. Cheng, Aaron Martin, Christopher Mozak, Pavan Kumar Kappagantula, Hsien-Pao Yang
  • Memory controller and memory system for suppression of fluctuation of voltage drop
    Patent number: 10672472
    Abstract: Provided is an initialization control unit that causes a resistance value of a variable resistive element in an access restriction region to be changed to an initial value larger than a predetermined value. The resistance value is changed in a read only mode among the read only mode in which writing to the access restriction region is prohibited and a writable mode in which the writing to the access restriction region is permitted. The access restriction region is in a memory cell array in which the variable resistive elements are arranged, and the initialization control unit transitions to the writable mode. In addition, a write control unit causes a resistance value of an element corresponding to write data among the variable resistive elements in the access restriction region to be changed to a value smaller than the initial value in the writable mode, and transitions to the read only mode.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: June 2, 2020
    Assignee: Sony Corporation
    Inventor: Haruhiko Terada
  • Semiconductor memory device including three-dimensional memory cell arrays
    Patent number: 10672794
    Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: June 2, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Fumihiro Kono
  • Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits
    Patent number: 10665294
    Abstract: A method of operating a semiconductor device powered by a first power supply potential can include generating a first voltage signal having a first logic level in response to a voltage detector circuit detecting that the first power supply potential is essentially lower than a predetermined voltage; latching the first voltage signal to provide a first latched voltage signal; generating at least one read or write assist signal having a read or write assist enable logic level in response to the first latched voltage signal; and altering a read or write operation to a static random access memory (SRAM) cell in response to the at least one read or write assist signal having the read or write assist enable logic level as compared to when the at least one read or write assist signal has a read or write assist disable logic level.
    Type: Grant
    Filed: October 27, 2018
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Darryl G. Walker
  • Nonvolatile semiconductor memory including a read operation
    Patent number: 10658039
    Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: May 19, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Iwai, Hiroshi Nakamura
  • Semiconductor memory device having memory cell pairs defining data based on threshold voltages
    Patent number: 10658031
    Abstract: To provide a semiconductor memory device capable of storing multi-value data while suppressing an increase in the threshold voltage set for a memory cell. A semiconductor memory device according to an embodiment includes a plurality of memory cell pairs, each having a first memory cell and a second memory cell. The first memory cell is configured so as to set at least one threshold voltage, whereas the second memory cell is configured so as to set a plurality of threshold voltages. Data stored in the memory cell pairs is defined using differences between the threshold voltages of the second memory cell and the threshold voltage of the first memory cell.
    Type: Grant
    Filed: August 25, 2018
    Date of Patent: May 19, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Hirokazu Nagase
  • Multi-level sensing circuit configured to use a bit line charge
    Patent number: 10650867
    Abstract: A multi-level sensing circuit for a multi-level memory device configured to “recognize” more than two different voltages. The multi-level voltage sensing circuit may include a pre-charge controller configured to pre-charge a pair of bit lines with a bit-line pre-charge voltage level in response to an equalizing signal during a sensing mode. The multi-level voltage sensing circuit may include a read controller configured to maintain a voltage of the pair of bit lines at the bit-line pre-charge voltage level in response to a read control signal during a sensing operation. The multi-level voltage sensing circuit may include a sense-amplifier configured to generate data of the pair of bit lines during the sensing mode. The multi-level voltage sensing circuit may include a voltage sensor configured to generate the equalizing signal by comparing a bit-line voltage with a reference voltage.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: May 12, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyung Sik Won, Tae Hun Kim
  • Magnetic memory device and writing method that achieves different resistance states with unidirectional voltages
    Patent number: 10650876
    Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistive element including first and second magnetic layers, and a nonmagnetic layer between the first and the second magnetic layers and capable of setting one of a first state in which magnetization directions of the first and second magnetic layers are parallel and a second state in which magnetization directions of the first and second magnetic layers are antiparallel, and a write circuit that applies a first voltage to the element when setting one of the first and second states to the element and applies a second voltage in a same direction as the first voltage and greater than the first voltage to the element when setting the other one of the first and second states to the element.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi Fujimori